Invention Application
- Patent Title: STRUCTURED INTEGRATED CIRCUIT DEVICE
- Patent Title (中): 结构化集成电路器件
-
Application No.: PCT/US2005026227Application Date: 2005-07-25
-
Publication No.: WO2006014849A3Publication Date: 2006-06-15
- Inventor: KAPEL ALON , GRIGORE GEORGE CATALIN , OR-BACH ZVI , AVRAM PETRICA , IACOBUT ROMEO , APOSTOL ADRIAN , WURMAN ZE EV , LEVENTHAL ADAM , ZEMAN RICHARD
- Applicant: EASIC CORP , KAPEL ALON , GRIGORE GEORGE CATALIN , OR-BACH ZVI , AVRAM PETRICA , IACOBUT ROMEO , APOSTOL ADRIAN , WURMAN ZE EV , LEVENTHAL ADAM , ZEMAN RICHARD
- Assignee: EASIC CORP,KAPEL ALON,GRIGORE GEORGE CATALIN,OR-BACH ZVI,AVRAM PETRICA,IACOBUT ROMEO,APOSTOL ADRIAN,WURMAN ZE EV,LEVENTHAL ADAM,ZEMAN RICHARD
- Current Assignee: EASIC CORP,KAPEL ALON,GRIGORE GEORGE CATALIN,OR-BACH ZVI,AVRAM PETRICA,IACOBUT ROMEO,APOSTOL ADRIAN,WURMAN ZE EV,LEVENTHAL ADAM,ZEMAN RICHARD
- Priority: US89902004 2004-07-27; US18692305 2005-07-22
- Main IPC: H03K19/173
- IPC: H03K19/173
Abstract:
A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
Information query
IPC分类:
