公开(公告)号：WO2006014849A3

公开(公告)日：2006-06-15

申请号：PCT/US2005026227

申请日：2005-07-25

Applicant: EASIC CORP ,  KAPEL ALON ,  GRIGORE GEORGE CATALIN ,  OR-BACH ZVI ,  AVRAM PETRICA ,  IACOBUT ROMEO ,  APOSTOL ADRIAN ,  WURMAN ZE EV ,  LEVENTHAL ADAM ,  ZEMAN RICHARD

Inventor： KAPEL ALON ,  GRIGORE GEORGE CATALIN ,  OR-BACH ZVI ,  AVRAM PETRICA ,  IACOBUT ROMEO ,  APOSTOL ADRIAN ,  WURMAN ZE EV ,  LEVENTHAL ADAM ,  ZEMAN RICHARD

IPC: H03K19/173

CPC classification number: H03K19/1776 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract translation: 可配置逻辑阵列可以包括：多个逻辑单元，其包含查找表; 覆盖多个逻辑单元的可定制金属和通孔连接层; 多种器件可定制的I / O单元; 多种配置可定制RAM块; 具有可定制内容的ROM块; 以及一个具有可定制I / O的微处理器，用于配置和测试阵列，其中定制全部在单个通孔层完成。

公开(公告)号：WO2006014849A2

公开(公告)日：2006-02-09

申请号：PCT/US2005/026227

申请日：2005-07-25

Applicant: EASIC CORPORATION ,  KAPEL, Alon ,  GRIGORE, George, Catalin ,  OR-BACH, Zvi ,  AVRAM, Petrica ,  IACOBUT, Romeo ,  APOSTOL, Adrian ,  WURMAN, Ze'ev ,  LEVENTHAL, Adam ,  ZEMAN, Richard

Inventor： KAPEL, Alon ,  GRIGORE, George, Catalin ,  OR-BACH, Zvi ,  AVRAM, Petrica ,  IACOBUT, Romeo ,  APOSTOL, Adrian ,  WURMAN, Ze'ev ,  LEVENTHAL, Adam ,  ZEMAN, Richard

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract translation: 可配置的逻辑阵列可以包括：多个逻辑单元，其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器，用于配置和测试阵列，其中的定制都在单个通孔层上完成。