Invention Application
- Patent Title: PRINTED CIRCUIT PATTERNED EMBEDDED CAPACITANCE LAYER
- Patent Title (中): 印刷电路图案化嵌入电容层
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Application No.: PCT/US2006005839Application Date: 2006-02-17
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Publication No.: WO2006101638B1Publication Date: 2007-02-15
- Inventor: DUNN GREGORY J , CROSWELL ROBERT T , MAGERA JAROSLAW A , SAVIC JOVICA , TUNGARE AROON V
- Applicant: MOTOROLA INC , DUNN GREGORY J , CROSWELL ROBERT T , MAGERA JAROSLAW A , SAVIC JOVICA , TUNGARE AROON V
- Assignee: MOTOROLA INC,DUNN GREGORY J,CROSWELL ROBERT T,MAGERA JAROSLAW A,SAVIC JOVICA,TUNGARE AROON V
- Current Assignee: MOTOROLA INC,DUNN GREGORY J,CROSWELL ROBERT T,MAGERA JAROSLAW A,SAVIC JOVICA,TUNGARE AROON V
- Priority: US8493805 2005-03-21
- Main IPC: H01L21/302
- IPC: H01L21/302
Abstract:
A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.
Public/Granted literature
- WO2006101638A2 PRINTED CIRCUIT PATTERNED EMBEDDED CAPACITANCE LAYER Public/Granted day:2006-09-28
Information query
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