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    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD
    3.
    发明申请
    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD 审中-公开
    在印刷电路板上制作封闭VIAS的方法

    公开(公告)号：WO2008057717B1

    公开(公告)日：2008-09-18

    申请号：PCT/US2007081343

    申请日：2007-10-15

    Applicant: MOTOROLA INC ,  MAGERA JAROSLAW A ,  DUNN GREGORY J ,  LEGANSKI KATHY D

    Inventor： MAGERA JAROSLAW A ,  DUNN GREGORY J ,  LEGANSKI KATHY D

    IPC: H01R12/04 ,  H05K1/11

    CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49165

    Abstract: A method for forming closed vies In a mgtfflayßr printed circuit board. A dielectric layer Is laminated to one side of a central. core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vtas In the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that Is much smaller In diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hols. Approximately one half of the closed vlas are situated such that the closed aperture faces one dielectric layer and a remainder of the dosed vias are situated such that the closed aperture faces the other dielectric layer.

    Abstract translation: 一种形成封闭的威胁的方法在一个mgtfflayßr印刷电路板中。 介电层被层压到中心的一侧。 芯在每侧具有金属层。 第二电介质层被层压到中心芯的另一侧。 封闭的Vtas中心芯是通过部分穿过但不完全穿透中心芯而形成的，然后从相对侧完成通孔，该孔的直径要小得多，以形成完全穿透中心芯的通道 从一边到另一边。 然后通孔用金属镀以基本上封闭较小的霍尔。 大约一半的闭合孔被定位成使得闭合孔面对一个电介质层，并且其余的经过定型的通孔被设置成使得闭合孔面对另一介电层。

    CAPACITANCE LAMINATE AND PRINTED CIRCUIT BOARD APPARATUS AND METHOD
    4.
    发明申请
    CAPACITANCE LAMINATE AND PRINTED CIRCUIT BOARD APPARATUS AND METHOD 审中-公开
    电容层压板和印刷电路板装置及方法

    公开(公告)号：WO2007078947A2

    公开(公告)日：2007-07-12

    申请号：PCT/US2006048473

    申请日：2006-12-19

    Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  MAGERA JAROSLAW A ,  SAVIC JOVICA

    Inventor： DUNN GREGORY J ,  MAGERA JAROSLAW A ,  SAVIC JOVICA

    IPC: H05K1/11 ,  H01R12/04

    CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718

    Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

    Abstract translation: 一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。 嵌入式电容印刷电路板组件包括两个嵌入的电容结构（110）。 每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。 可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。 主轴通孔（525）可以通过内层和外层形成。 多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD
    5.
    发明申请
    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD 审中-公开
    在印刷电路板上制造封闭VIAS的方法

    公开(公告)号：WO2008057717A3

    公开(公告)日：2008-07-31

    申请号：PCT/US2007081343

    申请日：2007-10-15

    Applicant: MOTOROLA INC ,  MAGERA JAROSLAW A ,  DUNN GREGORY J ,  LEGANSKI KATHY D

    Inventor： MAGERA JAROSLAW A ,  DUNN GREGORY J ,  LEGANSKI KATHY D

    IPC: H01R12/04 ,  H05K1/11

    CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49165

    Abstract: A method for forming closed vies In a mgtfflayßr printed circuit board. A dielectric layer Is laminated to one side of a central. core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vtas In the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that Is much smaller In diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hols. Approximately one half of the closed vlas are situated such that the closed aperture faces one dielectric layer and a remainder of the dosed vias are situated such that the closed aperture faces the other dielectric layer.

    Abstract translation: 一种在mgtfflayßr印刷电路板上形成闭合点的方法。 电介质层被层压到中央的一侧。 核心在每侧具有金属层。 第二介电层被层压到中央芯的另一侧。 在中央核心已形成部分穿过，但不是完全穿透中央核心，然后完成通孔从另一侧有一个小得多的直径，以形成完全穿透中央核心的通道 从一边到另一边。 然后通孔镀上金属以基本上封闭较小的玻璃管。 大约一半的封闭瓦片的位置使得封闭孔隙面向一个介电层并且其余的配料过孔的位置使得封闭孔隙面向另一个介电层。

    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD
    6.
    发明申请
    METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD 审中-公开
    在印刷电路板上制作封闭VIAS的方法

    公开(公告)号：WO2008057717A2

    公开(公告)日：2008-05-15

    申请号：PCT/US2007/081343

    申请日：2007-10-15

    Applicant: MOTOROLA, INC. ,  MAGERA, Jaroslaw, A. ,  DUNN, Gregory, J. ,  LEGANSKI, Kathy, D.

    Inventor： MAGERA, Jaroslaw, A. ,  DUNN, Gregory, J. ,  LEGANSKI, Kathy, D.

    IPC: H05K3/30 ,  H01L21/4763

    CPC classification number: H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49165

    Abstract: A method for forming closed vias in a multilayer printed circuit board. A dielectric layer (1085) is laminated to one side of a central core having a metal layer (120, 130) on each side. A second dielectric layer (1080) is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture (355) faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture (350) faces the other dielectric layer. Resin from one dielectric layer (1085) fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer (1080) fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

    Abstract translation: 一种在多层印刷电路板中形成封闭通孔的方法。 电介质层（1085）被层压到每侧具有金属层（120,130）的中心芯的一侧。 第二电介质层（1080）层压到中心芯的另一侧。 已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路 从一边到另一边。 然后通孔用金属电镀以基本上闭合较小的孔。 闭合通孔的大约一半被定位成使得闭合孔（355）面向一个电介质层，并且其余的封闭通孔被定位成使得闭合孔（350）面向另一介电层。 来自一个电介质层（1085）的树脂填充了大约一半的封闭通孔的空腔，并且来自另一介电层（1080）的树脂填充了其余的封闭通孔的圆形空腔。 从每个介电层迁移到封闭通孔中的树脂的总量近似相等。

    CAPACITANCE LAMINATE AND PRINTED CIRCUIT BOARD APPARATUS AND METHOD
    7.
    发明申请
    CAPACITANCE LAMINATE AND PRINTED CIRCUIT BOARD APPARATUS AND METHOD 审中-公开

    公开(公告)号：WO2007078947A3

    公开(公告)日：2007-07-12

    申请号：PCT/US2006/048473

    申请日：2006-12-19

    Applicant: MOTOROLA, INC. ,  DUNN, Gregory, J. ,  MAGERA, Jaroslaw, A. ,  SAVIC, Jovica

    Inventor： DUNN, Gregory, J. ,  MAGERA, Jaroslaw, A. ,  SAVIC, Jovica

    IPC: H05K1/11

    Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

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