Invention Application
WO2008057717A3 METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD
审中-公开
在印刷电路板上制造封闭VIAS的方法
- Patent Title: METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD
- Patent Title (中): 在印刷电路板上制造封闭VIAS的方法
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Application No.: PCT/US2007081343Application Date: 2007-10-15
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Publication No.: WO2008057717A3Publication Date: 2008-07-31
- Inventor: MAGERA JAROSLAW A , DUNN GREGORY J , LEGANSKI KATHY D
- Applicant: MOTOROLA INC , MAGERA JAROSLAW A , DUNN GREGORY J , LEGANSKI KATHY D
- Assignee: MOTOROLA INC,MAGERA JAROSLAW A,DUNN GREGORY J,LEGANSKI KATHY D
- Current Assignee: MOTOROLA INC,MAGERA JAROSLAW A,DUNN GREGORY J,LEGANSKI KATHY D
- Priority: US55769006 2006-11-08
- Main IPC: H01R12/04
- IPC: H01R12/04 ; H05K1/11
Abstract:
A method for forming closed vies In a mgtfflayßr printed circuit board. A dielectric layer Is laminated to one side of a central. core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vtas In the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that Is much smaller In diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hols. Approximately one half of the closed vlas are situated such that the closed aperture faces one dielectric layer and a remainder of the dosed vias are situated such that the closed aperture faces the other dielectric layer.
Public/Granted literature
- WO2008057717B1 METHOD FOR FABRICATING CLOSED VIAS IN A PRINTED CIRCUIT BOARD Public/Granted day:2008-09-18
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