Invention Application
- Patent Title: PROCESS OF SEMICONDUCTOR FABRICATION WITH MASK OVERLAY ON PITCH MULTIPLIED FEATURES AND ASSOCIATED STRUCTURES
- Patent Title (中): 半导体制造工艺与面罩叠加特征及相关结构
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Application No.: PCT/US2008/070932Application Date: 2008-07-23
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Publication No.: WO2009018059A2Publication Date: 2009-02-05
- Inventor: TRAN, Luan, C.
- Applicant: MICRON TECHNOLOGY, INC. , TRAN, Luan, C.
- Applicant Address: 8000 South Federal Way P.O. Box 6 Boise, ID 83707 US
- Assignee: MICRON TECHNOLOGY, INC.,TRAN, Luan, C.
- Current Assignee: MICRON TECHNOLOGY, INC.,TRAN, Luan, C.
- Current Assignee Address: 8000 South Federal Way P.O. Box 6 Boise, ID 83707 US
- Agency: ALTMAN, Daniel, E.
- Priority: US11/831,012 20070731
- Main IPC: H01L21/027
- IPC: H01L21/027
Abstract:
Spacers (175) are formed by pitch multiplication and a layer of negative photoresist (200) is deposited on and over the spacers (175) to form additional mask features. The deposited negative photoresist layer (200) is patterned, thereby removing photoresist from between the spacers (175) in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers (175) is facilitated. The pattern defined by the spacers (175) and the patterned negative photoresist is transferred to one or more underlying masking layers (130), (140) before being transferred to a substrate (110).
Information query
IPC分类:
