公开(公告)号：WO2009079517A2

公开(公告)日：2009-06-25

申请号：PCT/US2008/087029

申请日：2008-12-16

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/336 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

Abstract translation: 半导体材料的连续环路的不同部分彼此电隔离。 在一些实施例中，环路的端部与环路的中间部分电隔离。 在一些实施例中，具有在其端部连接在一起的两个腿的半导体材料的环通过间距倍增过程形成，其中间隔物环形成在心轴的侧壁上。 去除心轴并且将一块掩模材料覆盖在间隔环的至少一端上。 在一些实施例中，掩模材料块覆盖间隔环的每一端。 由间隔物和块限定的图案被转移到半导体材料层。 这些块将所有环路电连接在一起。 沿循环的每条腿形成选择门。 这些块作为源/排水沟。 选择门被偏置在关闭状态以防止电流从环路的中部流向块，从而将中间部分与环的端部电隔离，并且还将环的不同的腿与每个 其他。

公开(公告)号：WO2005029570A1

公开(公告)日：2005-03-31

申请号：PCT/US2004/030367

申请日：2004-09-16

Applicant: MICRON TECHNOLOGY, INC ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/336

CPC classification number: H01L27/10876 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

Abstract: Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Poly-silicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

Abstract translation: 公开了自对准凹陷门结构和形成方法。 首先在半导体衬底中形成用于隔离的场氧化物区域。 多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。 然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。 进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。 进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。 然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。

公开(公告)号：WO2009018059A2

公开(公告)日：2009-02-05

申请号：PCT/US2008/070932

申请日：2008-07-23

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  H01L21/0337

Abstract: Spacers (175) are formed by pitch multiplication and a layer of negative photoresist (200) is deposited on and over the spacers (175) to form additional mask features. The deposited negative photoresist layer (200) is patterned, thereby removing photoresist from between the spacers (175) in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers (175) is facilitated. The pattern defined by the spacers (175) and the patterned negative photoresist is transferred to one or more underlying masking layers (130), (140) before being transferred to a substrate (110).

Abstract translation: 通过间距倍增形成间隔物（175），并且在间隔物（175）上和上方沉积负光致抗蚀剂（200）层以形成额外的掩模特征。 沉积的负光致抗蚀剂层（200）被图案化，由此在一些区域中从间隔物（175）之间去除光致抗蚀剂。 在图案化期间，不需要将光引导至需要去除负光刻胶的区域，并且促进从间隔物（175）之间清洁去除负光刻胶。 在被转移到衬底（110）之前，由间隔物（175）和图案化的负性光刻胶限定的图案被转移到一个或多个下面的掩模层（130），（140）。

公开(公告)号：WO2009020773A2

公开(公告)日：2009-02-12

申请号：PCT/US2008/071031

申请日：2008-07-24

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract translation: 制造包含与有源区特征对准的紧密间距接触并且使用各种技术来定义具有亚光刻尺寸的图案的同时制造自对准紧间距接触和导线的半导体结构的方法。 还公开了具有与有源区特征对齐的紧密间距触点的半导体结构以及任选地对准的导电线，半导体结构也具有紧密间距接触孔和用于导电线的对准沟槽。

公开(公告)号：WO2009017982A2

公开(公告)日：2009-02-05

申请号：PCT/US2008/070407

申请日：2008-07-18

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C. ,  GIRIDHAR, Raghupathy

Inventor： TRAN, Luan, C. ,  GIRIDHAR, Raghupathy

IPC: H01L21/027

CPC classification number: H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/1052

Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

Abstract translation: 用于通过反向间距减小流程进行器件制造的方法的实施例包括在形成第一特征图案之后形成衬底上方的特征的第一图案并形成间距倍数间隔物的第二图案。 在本发明的实施例中，特征的第一图案可以通过光刻形成，并且间距倍增间隔物的第二图案可以通过间距倍增形成。 提供了其他用于器件制造的方法。

公开(公告)号：WO2007027558A2

公开(公告)日：2007-03-08

申请号：PCT/US2006/033421

申请日：2006-08-28

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C.

Inventor： TRAN, Luan, C.

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/8239

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/11521

Abstract: Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts (732), for example. In some embodiments, contacts (732) can be formed by providing an insulating layer (334) that is overlaid by multiple layers of masking material. A series of selectively definable lines (124) can then be created in the masking material, where the lines have a pattern. Pitch reduction can then be performed on the lines using a spacer material (170) to create pitch-reduced masking lines (175) that are elongate along a spacer axis. Each pitch-reduced masking line (175) can thus be separated by a pitch-reduced space. A second pattern (e.g., that of the second mask 480) of photoresist that crosses a portion of the masking features can then be applied. The second pattern can have a window (482) that leaves multiple portions of the pitch-reduced masking lines (175) and adjacent pitch-reduced spaces uncovered by the photoresist. The window (482) can have an elongate axis that is not parallel to the elongate axis of the pitch-reduced masking lines. The insulating layer (334) can then be etched through a third pattern-defined, in part, by the pitch-reduced spaces-to create contact vias (584) in the insulating layer (334). The contact vias (584) can be filled with a conductive material to create electrical contacts (732).

Abstract translation: 公开了形成用于集成电路的导电和/或半导体特征的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 这些特征可以在一个方向上具有减小的间距，在另一方向上可以具有较宽的间距。 常规的光刻步骤可以与俯仰减小技术组合使用，以形成例如细长的俯仰特征，例如位线接触（732）。 在一些实施例中，触点（732）可以通过提供由多层掩模材料覆盖的绝缘层（334）形成。 然后可以在掩模材料中产生一系列可选择定义的线（124），其中线具有图案。 然后可以使用间隔物材料（170）在线上执行节距减小，以产生沿间隔物轴线延伸的俯仰减小的掩蔽线（175）。 因此，每个节距减小的掩蔽线（175）可以​​由节距减小的空间分开。 然后可以施加穿过掩模特征的一部分的光致抗蚀剂的第二图案（例如，第二掩模480的图案）。 第二图案可以具有一个窗口（482），该窗口（482）使由减影掩模线（175）的多个部分和由光致抗蚀剂未覆盖的相邻节距减小的空间留下。 窗口（482）可以具有不平行于减音屏蔽线的细长轴线的细长轴线。 绝缘层（334）然后可以通过第三图案部分地被间距减小的空间来蚀刻，以在绝缘层（334）中形成接触孔（584）。 接触通孔（584）可以用导电材料填充以产生电触头（732）。

公开(公告)号：WO2006104634A3

公开(公告)日：2006-10-05

申请号：PCT/US2006/007333

申请日：2006-02-27

Applicant: MICRON TECHNOLOGY, INC. ,  TRAN, Luan, C. ,  LEE, John ,  LIU, Zengtao ,  FREEMAN, Eric ,  NIELSEN, Russell

Inventor： TRAN, Luan, C. ,  LEE, John ,  LIU, Zengtao ,  FREEMAN, Eric ,  NIELSEN, Russell

IPC: H01L21/311 ,  H01L21/033

Abstract: A method for defining patterns in an integrated circuit (100) comprises defining a plurality of features in a first photoresist layer using photolithography over a first region (102) of a substrate (108). The method further comprises using pitch multiplication to produce at least two features (120) in a lower masking layer (116) for each feature in the photoresist layer. The features in the lower masking layer (116) include looped ends (124). The method further comprises covering with a second photoresist layer (126) a second region (104) of the substrate (108) including the looped ends (124) in the lower masking layer (116). The method further comprises etching a pattern of trenches in the substrate (108) through the features in the lower masking layer without etching in the second region (104). The trenches have a trench width.

公开(公告)号：WO2019133277A1

公开(公告)日：2019-07-04

申请号：PCT/US2018/065462

申请日：2018-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WELLS, David, H. ,  TRAN, Luan, C. ,  LI, Jie ,  KHANDEKAR, Anish, A. ,  SHROTRI, Kunal

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/792 ,  H01L29/788

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a) : lower oxygen diffusivity than the first material, (b) : net positive charge, and (c) : at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

公开(公告)号：WO2005117121A2

公开(公告)日：2005-12-08

申请号：PCT/US2005/014466

申请日：2005-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TRAN, Luan, C. ,  FISHBURN, Fred, D.

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/24 ,  Y10S257/906 ,  Y10S257/908

Abstract: The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.

Abstract translation: 本发明包括可用于形成存储器阵列的存储器阵列和方法。 在存储器阵列制造期间可以使用图案化蚀刻停止件，其中蚀刻停止覆盖存储节点接触位置，同时将开口留在位线接触位置。 可以在蚀刻停止点上方和位线接触位置上形成绝缘材料，并且可以通过绝缘材料形成沟槽。 可以在沟槽内提供导电材料以形成与位线接触位置电接触的位线互连线，并且通过蚀刻停止件与存储节点接触位置电隔离。 在随后的处理中，可以通过蚀刻停止件向存储节点接触位置形成开口。 然后可以在开口内形成存储器存储装置，并与存储节点接触位置电接触。

公开(公告)号：WO2005109491A1

公开(公告)日：2005-11-17

申请号：PCT/US2005/014951

申请日：2005-04-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TRAN, Luan, C. ,  FISHBURN, Fred, D.

IPC: H01L21/768

CPC classification number: H01L21/7681 ,  H01L21/76895 ,  H01L21/823475

Abstract: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.

Abstract translation: 本发明包括用于形成与半导体结构相关联的电连接的方法。 提供了一种在其上具有导线的半导体衬底，并且具有与导电线相邻的至少两个扩散区域。 在扩散区域上形成图案化的蚀刻停止层。 图案化蚀刻停止件具有延伸穿过其的一对开口，其中开口沿着大致平行于该线的轴线。 在蚀刻停止点上形成绝缘材料。 绝缘材料暴露于蚀刻以在绝缘材料内形成沟槽，并且将开口从蚀刻停止件延伸到扩散区域。 沟槽的至少一部分直接在开口上方并且沿着线的轴线延伸。 在开口内和沟槽内形成导电材料。