发明申请
WO2012042292A1 METHODS FOR PROCESSING A SEMICONDUCTOR WAFER, A SEMICONDUCTOR WAFER AND A SEMICONDUCTOR DEVICE
审中-公开
加工半导体波形的方法,半导体波导和半导体器件
- 专利标题: METHODS FOR PROCESSING A SEMICONDUCTOR WAFER, A SEMICONDUCTOR WAFER AND A SEMICONDUCTOR DEVICE
- 专利标题(中): 加工半导体波形的方法,半导体波导和半导体器件
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申请号: PCT/IB2010/003017申请日: 2010-09-30
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公开(公告)号: WO2012042292A1公开(公告)日: 2012-04-05
- 发明人: RENAUD, Philippe , SERRANO, Roland
- 申请人: FREESCALE SEMICONDUCTOR, INC. , RENAUD, Philippe , SERRANO, Roland
- 申请人地址: 6501 William Cannon Drive West Austin, TX 78735 US
- 专利权人: FREESCALE SEMICONDUCTOR, INC.,RENAUD, Philippe,SERRANO, Roland
- 当前专利权人: FREESCALE SEMICONDUCTOR, INC.,RENAUD, Philippe,SERRANO, Roland
- 当前专利权人地址: 6501 William Cannon Drive West Austin, TX 78735 US
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L21/302 ; H01L21/78
摘要:
A method for processing a semiconductor wafer comprises providing the semiconductor wafer, which has a curvature in at least one direction. The curvature is reduced, which comprises providing in inactive areas of the semiconductor wafer multiple trench lines extending at least partially in a stressed layer of the semiconductor wafer and in parallel with the surface of the stressed layer. The multiple trench lines having a depth less than the thickness of the semiconductor wafer. A semiconductor wafer, comprising multiple active areas suitable for providing semiconductor devices or circuits. Inactive areas separate the active areas from each other. The wafer has a stressed layer with a first surface, and another layer which is in contact with the stressed layer along a second surface of the stressed layer, opposite to the first surface. Multiple trench lines, extend in parallel to the first surface of the stressed layer in an inactive area and have a depth less than the thickness of the semiconductor wafer.
IPC分类: