Invention Application
WO2015112272A1 METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES
审中-公开
用于形成具有紧密间距互连结构的互连层的方法
- Patent Title: METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES
- Patent Title (中): 用于形成具有紧密间距互连结构的互连层的方法
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Application No.: PCT/US2014/069355Application Date: 2014-12-09
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Publication No.: WO2015112272A1Publication Date: 2015-07-30
- Inventor: JEZEWSKI, Christopher J. , CHAWLA, Jasmeet S. , SINGH, Kanwal Jit , MYERS, Alan M. , TAN, Eliot N. , SCHENKER, Richard E.
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: WINKLE, Robert G.
- Priority: US14/163,323 20140124
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/31
Abstract:
Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.
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