公开(公告)号：WO2022066299A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/044884

申请日：2021-08-06

Applicant: INTEL CORPORATION

Inventor： DUONG, Benjamin ,  GARELICK, Michael ,  GRUJICIC, Darko ,  IBRAHIM, Tarek ,  MARIN, Brandon C. ,  VADLAMANI, Sai ,  WALL, Marcel

IPC: H01L23/64 ,  H05K1/02 ,  H01L49/02

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：WO2019245684A1

公开(公告)日：2019-12-26

申请号：PCT/US2019/033039

申请日：2019-05-20

Applicant: INTEL CORPORATION

Inventor： ELSHERBINI, Adel ,  EID, Feras ,  SWAN, Johanna

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/36

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.

公开(公告)号：WO2019112582A1

公开(公告)日：2019-06-13

申请号：PCT/US2017/065062

申请日：2017-12-07

Applicant: INTEL CORPORATION

Inventor： LIMAYE, Ameya ,  MANI, Divya

IPC: H01L23/367 ,  H01L23/373

Abstract: An integrated circuit structure may be fabricated to include a dam structure to contain a thermal interface material between a back surface of an integrated circuit device and a heat dissipation device. The use of the dam structure may significantly reduce pump-out of the thermal interface material during assembly and/or operation, and, thus, may prevent the formation of air-gaps, which can increase thermal resistance.

公开(公告)号：WO2018222187A1

公开(公告)日：2018-12-06

申请号：PCT/US2017/035273

申请日：2017-05-31

Applicant: INTEL CORPORATION

Inventor： WENG, Li-Sheng ,  CHEN, Chung-Hao ,  MATAYABAS, JR., James C. ,  TANG, Min Keen

IPC: H01L23/552 ,  H01L23/00

Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.

公开(公告)号：WO2017189119A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/023114

申请日：2017-03-19

Applicant: INTEL CORPORATION

Inventor： EID, Feras ,  SANKMAN, Robert L. ,  SANE, Sandeep B.

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/485 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

Abstract translation: 可以制造微电子封装，其具有至少一个柔性外部接合焊盘，该至少一个柔性外部接合焊盘具有至少一个集成弹簧结构，用于减轻附连到外部基板期间微电子封装的翘曲的影响。 用于微电子封装的实施例可以包括具有第一表面和相对的第二表面的微电子封装衬底，其中微电子封装衬底包括限定在其中的空隙，其从第二表面延伸到微电子封装衬底中，并且柔性接合焊盘 其中所述柔性接合垫包括接地部分和至少一个弹簧部分，并且其中所述至少一个弹簧部分从所述柔性接合垫接合区部分延伸到所述微电子封装基板第二表面上的锚定结构。 / p>

公开(公告)号：WO2017171741A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/024866

申请日：2016-03-30

Applicant: INTEL CORPORATION

Inventor： SUNG, Seung Hoon ,  TURKOT, Robert B. ,  RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  RACHMADY, Willy ,  DASGUPTA, Sansaptak ,  KAVALIEROS, Jack T.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66659 ,  H01L29/66356 ,  H01L29/66636 ,  H01L29/7391

Abstract: The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.

Abstract translation: 本说明书涉及使用成角度蚀刻来制造微电子晶体管源极和/或漏极区域。 在一个实施例中，可以通过使用倾斜蚀刻来形成微电子晶体管以减少形成p型掺杂区域和n型掺杂区域所需的掩模步骤的数量。 在进一步的实施例中，成角度蚀刻可用于在晶体管栅极的相对侧上形成不对称间隔物，其中不对称间隔物可导致不对称的源极/漏极配置。

公开(公告)号：WO2017099788A1

公开(公告)日：2017-06-15

申请号：PCT/US2015/065165

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： LI, Eric ,  GOSSELIN, Timothy ,  TOMITA, Yoshihiro ,  LIFF, Shawna ,  EITAN, Amram ,  SALTAS, Mark

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/11002 ,  H01L2224/1182 ,  H01L2224/131 ,  H01L2224/14134 ,  H01L2224/14177 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/27002 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/14131 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/27

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Abstract translation: 微电子结构包括具有第一表面和从微电子衬底第一表面延伸到衬底中的空腔的微电子衬底，附着到微电子衬底第一表面的第一微电子器件和第二微电子器件， 以及布置在微电子衬底腔内并且附着到第一微电子器件和第二微电子器件的微电子桥。 在一个实施例中，微电子结构可以包括由第一微电子器件和第二微电子器件形成的重构晶片。 在另一个实施例中，焊剂材料可以在第一微电子器件和微电子桥之间以及第二微电子器件和微电子桥之间延伸。

公开(公告)号：WO2017039583A1

公开(公告)日：2017-03-09

申请号：PCT/US2015/047440

申请日：2015-08-28

Applicant: INTEL CORPORATION ,  CHEN, Chi-Mon ,  LI, Yi ,  WU, Tao ,  ZHOU, Zheng ,  SALAMA, Islam A. ,  LIU, Yueli ,  ALUR, Amruthavalli P. ,  SHARMA, Nikhil

Inventor： CHEN, Chi-Mon ,  LI, Yi ,  WU, Tao ,  ZHOU, Zheng ,  SALAMA, Islam A. ,  LIU, Yueli ,  ALUR, Amruthavalli P. ,  SHARMA, Nikhil

IPC: H01L25/07 ,  H01L23/48

CPC classification number: H01L21/481 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83104 ,  H01L2924/15159 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A microelectronic package may be fabricated by forming a microelectronic substrate having a front surface and a back surface, transferring thickness variation in the microelectronic substrate to the microelectronic substrate back surface by attaching the microelectronic substrate front surface to a first fixture, forming a sacrificial material over the microelectronic substrate back surface having a first surface opposing the microelectronic substrate back surface, removing the microelectronic substrate from the first substrate, attaching the sacrificial material first surface to a second fixture, and attaching at least one microelectronic device to the microelectronic substrate front surface. In another embodiment, a releasing layer may be disposed between the microelectronic substrate back surface and the sacrificial material.

Abstract translation: 可以通过形成具有前表面和后表面的微电子衬底来制造微电子封装，通过将微电子衬底前表面附接到第一固定件，将微电子衬底中的厚度变化传递到微电子衬底背面，从而形成牺牲材料 所述微电子衬底背表面具有与所述微电子衬底背表面相对的第一表面，从所述第一衬底移除所述微电子衬底，将所述牺牲材料第一表面附接到第二固定件，以及将至少一个微电子器件附接到所述微电子衬底前表面。 在另一个实施例中，释放层可以设置在微电子衬底背表面和牺牲材料之间。

公开(公告)号：WO2017023253A1

公开(公告)日：2017-02-09

申请号：PCT/US2015/043166

申请日：2015-07-31

Applicant: INTEL CORPORATION ,  KARPOV, Elijah V. ,  MAJHI, Prashant ,  KOTLYAR, Roza ,  MUKHERJEE, Niloy ,  KUO, Charles C. ,  SHAH, Uday ,  PILLARISETTY, Ravi ,  CHAU, Robert S.

Inventor： KARPOV, Elijah V. ,  MAJHI, Prashant ,  KOTLYAR, Roza ,  MUKHERJEE, Niloy ,  KUO, Charles C. ,  SHAH, Uday ,  PILLARISETTY, Ravi ,  CHAU, Robert S.

IPC: H01L29/02

CPC classification number: H01L29/02 ,  H01L27/0705 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/7869

Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

Abstract translation: 具有功能金属氧化物通道的微电子器件可以通过在微电子衬底和功能金属氧化物沟道之间形成缓冲过渡层而制成在微电子衬底上，该微电子衬底可用于非常大规模的集成，例如硅衬底。 在一个实施例中，微电子器件可以是具有形成在缓冲器过渡层上的源极结构和漏极结构的微电子晶体管，其中源极结构和漏极结构邻接功能金属氧化物沟道的相对侧并且设置栅极电介质 在栅电极和功能金属氧化物通道之间。 在另一个实施例中，微电子器件可以是双端微电子器件。

公开(公告)号：WO2016099509A1

公开(公告)日：2016-06-23

申请号：PCT/US2014/071163

申请日：2014-12-18

Applicant: INTEL CORPORATION ,  THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  GARDNER, Sanaz K. ,  SUNG, Seung Hoon ,  CHAU, Robert S.

Inventor： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  GARDNER, Sanaz K. ,  SUNG, Seung Hoon ,  CHAU, Robert S.

IPC: H01L29/778

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.

Abstract translation: 本说明书涉及包括凹陷栅电极的n沟道氮化镓晶体管，其中栅电极和氮化镓层之间的偏振层小于约1nm。 在另外的实施例中，n沟道氮化镓晶体管可以具有不对称配置，其中栅极 - 漏极长度大于栅极 - 源极长度。 在进一步的实施例中，与使用硅基晶体管的无线功率/充电装置相比，n沟道氮化镓晶体管可以用于无线功率/充电装置中，以提高效率，更长的传输距离和更小的形状因数。