Invention Application
WO2016010707A1 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED SYSTEMS
审中-公开
堆叠式半导体集成电路，具有高效率热性能和相关系统
- Patent Title: STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED SYSTEMS
- Patent Title (中): 堆叠式半导体集成电路，具有高效率热性能和相关系统
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Application No.: PCT/US2015/037685Application Date: 2015-06-25
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Publication No.: WO2016010707A1Publication Date: 2016-01-21
- Inventor: VADHAVKAR, Sameer, S. , LI, Xiao , GROOTHUIS, Steven, K. , LI, Jian , GANDHI, Jaspreet, S. , DEDDERIAN, James, M. , HEMBREE, David, R.
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: 8000 S. Federal Way, P.O. Box 6 Boise, ID 83707-0006 US
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: 8000 S. Federal Way, P.O. Box 6 Boise, ID 83707-0006 US
- Agency: TOLOMEI, John, G. et al.
- Priority: US14/330,934 20140714
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/48 ; H01L25/065 ; H01L25/07
Abstract:
A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
Information query
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