公开(公告)号：WO2007027880A2

公开(公告)日：2007-03-08

申请号：PCT/US2006/034011

申请日：2006-08-31

Applicant: MICRON TECHNOLOGY, INC. ,  OLIVER, Steven, D. ,  VELICKY, Lu ,  HIATT, William, M. ,  HEMBREE, David, R. ,  TUTTLE, Mark, E. ,  RIGG, Sidney ,  WARK, James ,  FARNWORTH, Warren, M. ,  KIRBY, Kyle

Inventor： OLIVER, Steven, D. ,  VELICKY, Lu ,  HIATT, William, M. ,  HEMBREE, David, R. ,  TUTTLE, Mark, E. ,  RIGG, Sidney ,  WARK, James ,  FARNWORTH, Warren, M. ,  KIRBY, Kyle

IPC: H01L27/146

CPC classification number: H01L21/00 ,  H01L21/76898 ,  H01L23/552 ,  H01L27/14609 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.

Abstract translation: 本文公开了用于在晶片级制造多个成像单元的微电子成像单元和方法。 在一个实施例中，制造多个成像单元的方法包括提供具有多个成像管芯的成像工件，所述成像管芯包括集成电路，电耦合到集成电路的外部触点以及可操作地耦合到集成电路的图像传感器。 各个图像传感器包括在图像传感器的周边部分处的至少一个暗电流像素。 该方法包括将覆盖层沉积在工件上并在图像传感器上方。 该方法还包括图案化和选择性地显影覆盖层以在对应的图像传感器上形成分离体积的覆盖层材料。 覆盖层材料的离散体积具有与各个暗电流像素的内侧边缘对准的侧壁，使得暗电流像素不被离散体积覆盖。

公开(公告)号：WO2021202038A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/020549

申请日：2021-03-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JENSEN, Travis, M. ,  HEMBREE, David, R.

IPC: H01L25/065 ,  H01L23/485 ,  H01L23/525 ,  H01L21/60 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L24/02 ,  H01L25/0657 ,  H01L25/50 ,  H01L2924/15311

Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

公开(公告)号：WO1996035129A1

公开(公告)日：1996-11-07

申请号：PCT/US1996006002

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WOOD, Alan, G. ,  FARNWORTH, Warren, M. ,  AKRAM, Salman ,  HEMBREE, David, R.

IPC: G01R31/02

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 用于测试未封装半导体晶片的方法和装置包括安装在母板（10）上的母板（10）和多个互连（12），并适于建立与芯片（14）的临时电连接。 互连（12）可以形成有用于接触管芯（14）的接合焊盘（22）的硅衬底（20）和凸起的接触构件（16）。 或者，互连（16）可以形成有安装在绝缘膜（74）上的微凸块接触构件（16）。 母板（10）允许每个模具（14）单独测试速度和功能，并且还可以使用标准老化炉并行测试。 在替代实施例中，使用母板/子板布置进行测试。 每个子板（82）包括允许骰子（14）单独测试速度和功能的互连（12）。 然后可以将多个子板（82）安装到母板（10）上，以使用标准老化烤箱进行老化测试。

公开(公告)号：WO2016010707A1

公开(公告)日：2016-01-21

申请号：PCT/US2015/037685

申请日：2015-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： VADHAVKAR, Sameer, S. ,  LI, Xiao ,  GROOTHUIS, Steven, K. ,  LI, Jian ,  GANDHI, Jaspreet, S. ,  DEDDERIAN, James, M. ,  HEMBREE, David, R.

IPC: H01L23/34 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。

公开(公告)号：WO2007133302A2

公开(公告)日：2007-11-22

申请号：PCT/US2007/002336

申请日：2007-01-29

Applicant: MICRON TECHNOLOGY, INC. ,  HEMBREE, David, R. ,  WOOD, Alan, G.

Inventor： HEMBREE, David, R. ,  WOOD, Alan, G.

IPC: H01J17/49

CPC classification number: H01L24/16 ,  G01R1/06716 ,  G01R1/07307 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02125 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/0333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45684 ,  H01L2224/45698 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/4899 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10155 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45164 ,  H01L2924/013 ,  H01L2924/00013

Abstract: A semiconductor component (10) includes a semiconductor substrate (12) having a substrate contact (20), and a through wire interconnect (TWI) (14) attached to the substrate contact (20). The through wire interconnect (14) provides a multi level interconnect having contacts (32, 48) on opposing first (17) and second (18) sides of the semiconductor substrate (12). The through wire interconnect (TWI) (14) includes a via (28) through the substrate contact (20) and the substrate (12), a wire (30) in the via (28) having a bonded connection (42) with the substrate contact (20), a first contact (32) on the wire proximate to the first side (17), and a second contact (46) on the wire (30) proximate to the second side (18). The through wire interconnect (TWI) (14) also includes a polymer layer (16) which partially encapsulates the through wire interconnect (TWI) (14) while leaving the first contact (32) exposed. The semiconductor component (10) can be used to fabricate stacked systems (54), module systems (74) and test systems (72). A method for fabricating the semiconductor component (10) can include a film assisted molding process for forming the polymer layer (16).

Abstract translation: 半导体部件（10）包括具有衬底接触件（20）的半导体衬底（12）和连接到衬底接触件（20）的通孔互连（TWI）（14）。 通线互连（14）提供在半导体衬底（12）的相对的第一（17）和第二（18）侧上具有触点（32,48）的多电平互连。 通线互连（TWI）（14）包括穿过基板接触件（20）和基板（12）的通孔（28），通孔（28）中的导线（30）具有接合连接（42） 基板触点（20），靠近第一侧（17）的导线上的第一触点（32）以及接近第二侧（18）的导线（30）上的第二触点（46）。 通孔互连（TWI）（14）还包括聚合物层（16），其在使第一接触（32）暴露的同时部分地封装通孔互连（TWI）（14）。 半导体部件（10）可用于制造堆叠系统（54），模块系统（74）和测试系统（72）。 制造半导体部件（10）的方法可以包括用于形成聚合物层（16）的膜辅助成型工艺。

公开(公告)号：WO1995028737A1

公开(公告)日：1995-10-26

申请号：PCT/US1995004690

申请日：1995-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  FARNWORTH, Warren, M. ,  FOLARON, Jennifer, L. ,  FOLARON, Robert, J. ,  HEMBREE, David, R. ,  JACOBSON, John, O. ,  NELSON, Jay, C. ,  WARREN, Lelan, D.

IPC: H01L21/00

CPC classification number: H01L21/67276 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2893 ,  G01R31/311 ,  H01L21/67126 ,  H01L21/67242 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/74 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K13/08 ,  Y10T29/49004 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: An apparatus for automatically positioning electronic die within temporary packages to enable continuity testing and the like between the die bond pads and the temporary package electrical interconnects is provided. The apparatus includes a robot having a programmable robot arm with a gripper assembly, die and lid feeder stations, a die inverter, and a plurality of cameras or image producers. The cameras take several pictures of the die and temporary packages to precisely align the die bond pads with the temporary package electrical interconnects. A predetermined assembly position is located along a conveyor that conveys a carrier between a first position, corresponding to an inlet, and a second position, corresponding to an outlet. The die, a restraining device and temporary package are assembled at the predetermined assembly position and tested for continuity therebetween. The apparatus further includes a fifth camera which locates the die at a wafer handler. The apparatus has a control mechanism including a microprocessor and associated program routines that selectively control the robot arm (i) to move the gripper assembly to the lid feeder station to pick up a lid, (ii) to move the gripper assembly along with the lid to pick up the die following photographing by the rough die camera, (iii) to move the gripper assembly along with the lid and the die to a position to be photographed by the fine die camera, and (iv) to move the lid and the die to the predetermined assembly position located along the conveyor. The method and apparatus may also be used for disassembly.

Abstract translation: 提供一种用于将电子管芯自动定位在临时封装内以使得管芯接合焊盘和临时封装电互连之间的连续性测试等的装置。 该装置包括具有可编程机器人臂的机器人，该机器人臂具有夹持器组件，模具和盖子馈送站，模具逆变器以及多个相机或图像生成器。 相机拍摄模具和临时包装的几张照片，以便将芯片接合焊盘与临时封装电气互连精确对准。 预定的组装位置沿着输送机定位，该输送器在对应于出口的第一位置（对应于入口）和第二位置之间输送载体。 模具，约束装置和临时包装组装在预定的组装位置，并测试其间的连续性。 该设备还包括一个将晶片定位在晶片处理器上的第五相机。 该装置具有包括微处理器和相关程序例程的控制机构，其选择性地控制机器人手臂（i）将夹持器组件移动到盖子馈送站以拾起盖子，（ii）沿着盖子移动夹持器组件 通过粗模相机拍摄后拾取模具，（iii）将夹具组合件与盖和模具一起移动到由精细模具相机拍摄的位置，以及（iv）移动盖子和 沿着输送机到达预定的组装位置。 该方法和装置也可以用于拆卸。

公开(公告)号：WO2012021338A3

公开(公告)日：2012-02-16

申请号：PCT/US2011/046315

申请日：2011-08-02

Applicant: MICRON TECHNOLOGY, INC. ,  SILLS, Scott, E. ,  JENKINS, David, R. ,  HEMBREE, David, R.

Inventor： SILLS, Scott, E. ,  JENKINS, David, R. ,  HEMBREE, David, R.

IPC: H01L33/64 ,  H01L33/02

Abstract: A solid state light ("SSL"), a solid state emitter ("SSE"), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate.

公开(公告)号：WO2010030474A1

公开(公告)日：2010-03-18

申请号：PCT/US2009/054313

申请日：2009-08-19

Applicant: MICRON TECHNOLOGY, INC. ,  FAY, Owen, R. ,  FARNWORTH, Warren, M. ,  HEMBREE, David, R.

Inventor： FAY, Owen, R. ,  FARNWORTH, Warren, M. ,  HEMBREE, David, R.

IPC: H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05611 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13687 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81898 ,  H01L2224/831 ,  H01L2224/83141 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract translation: 公开了用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法。 根据特定实施例的系统包括具有第一衬底材料的第一半导体衬底和由第一半导体衬底承载的穿透结构。 该系统还包括第二半导体衬底，该第二半导体衬底具有带有预制凹槽的第二衬底材料。 第一半导体衬底的穿透结构被容纳在第二半导体衬底的凹部中，并且与凹部机械地接合并固定到第二半导体衬底。

公开(公告)号：WO2004043680A2

公开(公告)日：2004-05-27

申请号：PCT/US2003/036745

申请日：2003-11-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FARNWORTH, Warren, M. ,  HIATT, William, M. ,  HEMBREE, David, R. ,  BENSON, Peter, A. ,  AHMAD, Syed, Sajid ,  HESS, Michael, E.

IPC: B29C67/00

CPC classification number: B29C64/35 ,  B29C64/135 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y50/02

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract translation: 编程材料合并装置包括与所述至少一个制造位置相关联的至少一个制造位置和材料固结系统。 至少一个制造位置可以被配置为接收一个或多个制造衬底，例如半导体衬底。 具有可移动或位置固定的照相机的机器视觉系统可以与至少一个制造场所和材料合并系统相关联。 清洁部件也可以与至少一个制造部位相关联。 清洁部件可以与至少一个制造部位共享一个或多个元件，或者可以与其分开。 编程材料合并装置还可以包括基板处理系统，其将制造基板放置在编程材料固结装置的适当位置。

公开(公告)号：WO2018075204A1

公开(公告)日：2018-04-26

申请号：PCT/US2017/053517

申请日：2017-09-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HEMBREE, David, R. ,  STEPHENSON, William, R.

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/07

Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.

Abstract translation: 具有高效率热路径和模制底部填充材料的半导体芯片组件。 在一个实施例中，半导体管芯组件包括第一管芯和多个第二管芯。 第一芯片具有第一功能，侧面区域和堆叠位置。 第二管芯具有与第一管芯不同的功能，并且第二管芯处于管芯堆叠中，该管芯堆叠包括安装到第一管芯的堆叠位置的底部第二管芯和限定管芯堆叠的顶部表面的顶部第二管芯。 热传递结构至少附接到第一模具的横向区域并且具有第二模具定位在其中的空腔。 底部填充材料位于第二芯片和热传导结构之间的空腔中，底部填充材料覆盖芯片堆叠的顶部表面。