Invention Application
- Patent Title: MICROELECTRONIC BUILD-UP LAYERS AND METHODS OF FORMING THE SAME
- Patent Title (中): 微电子建筑层及其形成方法
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Application No.: PCT/US2015/016072Application Date: 2015-02-16
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Publication No.: WO2016133489A1Publication Date: 2016-08-25
- Inventor: MARIN, Brandon C. , GHOSH DASTIDAR, Trina , LI, Yonggang , SENEVIRATNE, Dilan
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: WINKLE, Robert G.
- Main IPC: H01L21/768
- IPC: H01L21/768
Abstract:
A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.
Information query
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