公开(公告)号：WO2016133489A1

公开(公告)日：2016-08-25

申请号：PCT/US2015/016072

申请日：2015-02-16

Applicant: INTEL CORPORATION

Inventor： MARIN, Brandon C. ,  GHOSH DASTIDAR, Trina ,  LI, Yonggang ,  SENEVIRATNE, Dilan

IPC: H01L21/768

CPC classification number: H05K3/187 ,  H01L21/288 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H05K1/036 ,  H05K1/09 ,  H05K3/0032 ,  H05K3/105 ,  H05K3/182 ,  H05K2201/09036

Abstract: A build-up layer may be fabricated by forming a microelectronic dielectric layer comprising a dielectric material with a metallization catalyst dispersed therein, forming a primer layer on the microelectronic dielectric layer, and forming a recess through the primer layer and into the dielectric material layer. An activation layer may be formed in or on the exposed microelectronic dielectric layer within the recess, wherein the primer layer acts as a mask. A metal layer may be formed on the activation layer, such as with an electroless process. Thus, the resolution of the metal layer deposition may be precisely controlled by the process used to form the recess.

Abstract translation: 可以通过形成包含分散在其中的金属化催化剂的电介质材料的微电子介电层来形成堆积层，在微电子介电层上形成底漆层，以及通过底漆层形成凹陷并进入电介质材料层。 活化层可以形成在凹陷内的暴露的微电子介电层中或其上，其中底漆层用作掩模。 可以在活化层上形成金属层，例如用无电解方法。 因此，可以通过用于形成凹部的工艺来精确地控制金属层沉积的分辨率。

公开(公告)号：WO2023049540A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/073988

申请日：2022-07-21

Applicant: INTEL CORPORATION

Inventor： ECTON, Jeremy D. ,  ARANA, Leonel R. ,  MARIN, Brandon C. ,  PIETAMBARAM, Srinivas Venkata Ramanuja ,  DUAN, Gang

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/48 ,  H01L23/15 ,  H01L23/00 ,  H01L23/498 ,  H01L23/29

Abstract: An electronic device comprises a mold layer that includes multiple integrated circuit (IC) dice having contact pads, a glass core patch embedded in encapsulating material that surrounds the top, bottom, and sides of the glass core patch, and a first redistribution layer arranged between the first mold layer and the glass core patch. The first redistribution layer includes electrically conductive interconnect that electrically connects one or more contact pads of the IC dice to the glass core patch.

公开(公告)号：WO2023038786A1

公开(公告)日：2023-03-16

申请号：PCT/US2022/041126

申请日：2022-08-22

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  MALLIK, Debendra ,  IBRAHIM, Tarik A. ,  ECTON, Jeremy ,  KARHADE, Omkar G. ,  PENMECHA, Bharat Prasad ,  LI, Xiaoqian ,  DESHPANDE, Nitin A. ,  MODI, Mitul ,  NIE, Bai

IPC: H01L25/16 ,  G02B6/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/538 ,  H01L21/52

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

公开(公告)号：WO2023038755A1

公开(公告)日：2023-03-16

申请号：PCT/US2022/039973

申请日：2022-08-10

Applicant: INTEL CORPORATION

Inventor： TANAKA, Hiroki ,  MARIN, Brandon C. ,  DARMAWIKARTA, Kristof ,  PIETAMBARAM, Srinivas Venkata Ramanuja ,  ECTON, Jeremy D. ,  MAHALINGAM, Hari ,  DUONG, Benjamin

IPC: G02B6/12

Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.

公开(公告)号：WO2022260733A1

公开(公告)日：2022-12-15

申请号：PCT/US2022/019493

申请日：2022-03-09

Applicant: INTEL CORPORATION

Inventor： MARIN, Brandon C.

IPC: H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L23/528 ,  H01L23/13

Abstract: An electronic substrate may be fabricated having a primary interposer comprising a laminate with a metal via through the laminate, two or more secondary interposers attached to a first side of the primary interposer, where respective sidewalls of the two or more secondary interposers define one or more recesses over the primary interposer, and an embedded component within a recess of the one or more recesses defined by the respective sidewalls of the two or more secondary interposers. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

公开(公告)号：WO2022108647A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/049666

申请日：2021-09-09

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  PAITAL, Sameer ,  VADLIMANI, Sai ,  MANEPALLI, Rahul N. ,  LI, Xiaoqian ,  POTHUKUCHI, Suresh V. ,  SHARAN, Sujit ,  SARKAR, Arnab ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PRATAP, Divya ,  ECTON, Jeremy ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ZHANG, Zhichao ,  AYGÜN, Kemal ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  JAUSSI, James E. ,  GAMBA, Jason M. ,  CASPER, Bryan K. ,  DUAN, Gang ,  INTI, Rajesh ,  MANSURI, Mozhgan ,  JADHAV, Susheel ,  BROWN, Kenneth ,  AGRAWAL, Ankar ,  DOBRIYAL, Priyanka

IPC: G02B6/42 ,  H01L31/0203 ,  H01L23/538 ,  H01L25/16

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：WO2022066299A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/044884

申请日：2021-08-06

Applicant: INTEL CORPORATION

Inventor： DUONG, Benjamin ,  GARELICK, Michael ,  GRUJICIC, Darko ,  IBRAHIM, Tarek ,  MARIN, Brandon C. ,  VADLAMANI, Sai ,  WALL, Marcel

IPC: H01L23/64 ,  H05K1/02 ,  H01L49/02

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.