Invention Application
- Patent Title: SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES
- Patent Title (中): 微电子结构中互连垫的表面处理
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Application No.: PCT/US2015/017435Application Date: 2015-02-25
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Publication No.: WO2016137452A1Publication Date: 2016-09-01
- Inventor: PIETAMBARAM, Srinivas V. , LEE, Kyu Oh
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: WINKLE, Robert G.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065
Abstract:
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
Information query
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