A wafer-level packaging method for SOI-MEMS structures that are desired to be encapsulated in a hermetic cavity with electrical leads to the outside without destroying the hermeticity of the cavity. The MEMS devices and vertical feedthroughs are both fabricated on the same SOI wafer, whereas a glass or silicon wafer is used for capping and routing metallization. The method requires at most five process masks and a single SOI wafer. Compared to the existing packaging technologies it reduces the number of wafers, process masks, and process steps. Conventional wirebonding is sufficient to connect the vertical feedthroughs to the outer world, without a need for conductor-refill inside the via openings. The method is compatible with low-temperature thermo-compression-based bonding/sealing processes and also with the silicon-glass anodic or silicon-silicon fusion bonding processes, which do not require any sealing material for bonding/sealing. The simplified process increase the reliability and yield in addition to lowering the manufacturing costs of hermetically-sealed MEMS components with the present invention.