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    静电微机电系统换能器、制造方法及电子设备
    2.
    发明申请
    静电微机电系统换能器、制造方法及电子设备 审中-公开

    公开(公告)号：WO2023078212A1

    公开(公告)日：2023-05-11

    申请号：PCT/CN2022/128706

    申请日：2022-10-31

    申请人： 歌尔微电子股份有限公司

    发明人： 邹泉波

    IPC分类号： B81B7/02 ,  B81B7/00 ,  B81C1/00 ,  H04R19/00 ,  H04R19/04

    摘要： 一种静电微机电系统换能器、制造方法及电子设备，该静电微机电系统换能器包括：第一电极（36）；相对于第一电极（36）能移动的第二电极（32）；以及位于第一电极（36）和第二电极（32）之间的电介质层（35a、35b），其中，电介质层（35a、35b）包括标准部分（35a）和泄漏部分（35b），标准部分（35a）的材料是标准电介质材料，泄漏部分（35b）的材料是泄漏电介质材料。

    WINDOW CAVITY WAFERS
    5.
    发明申请
    WINDOW CAVITY WAFERS 审中-公开

    公开(公告)号：WO2023059634A1

    公开(公告)日：2023-04-13

    申请号：PCT/US2022/045669

    申请日：2022-10-04

    申请人： MATERION CORPORATION

    发明人： KELLER, Reto ,  KOBA, Richard

    IPC分类号： G01J5/02 ,  G01J5/04 ,  G01J5/20 ,  H01L31/09 ,  B81C1/00 ,  B81B7/00 ,  B23K1/005 ,  B81B7/0035 ,  B81C1/00317 ,  G01J2005/202 ,  G01J5/0235 ,  G01J5/024 ,  G01J5/045 ,  G01J5/0802

    摘要： Techniques and/or systems are disclosed herein for forming a window cavity wafer that includes fabricating a window wafer by: providing a window wafer substrate having two faces; etching fiducials onto one or more faces of the window wafer substrate; and applying one or more optical coatings to on one or more faces of the window wafer substrate. Next, fabricating a spacer wafer separate from the window wafer by: providing a spacer wafer substrate having two faces; and forming an array of through-holes in the spacer wafer substrate. Then, bonding the spacer wafer to the window wafer to form the window cavity wafer; and forming discrete metal frames on a face of the window cavity wafer.

    액적 흐름속도 제어표면의 제작방법 및 이의 방법으로 제작되는 액적 흐름속도 제어표면
    6.
    发明申请
    액적 흐름속도 제어표면의 제작방법 및 이의 방법으로 제작되는 액적 흐름속도 제어표면 审中-公开

    公开(公告)号：WO2023058898A1

    公开(公告)日：2023-04-13

    申请号：PCT/KR2022/012633

    申请日：2022-08-24

    申请人： 충남대학교산학협력단

    发明人： 강성민 ,  안준형 ,  최지성

    IPC分类号： B81C1/00 ,  B81B7/00 ,  B81B7/04 ,  G03F7/00 ,  B29C33/40 ,  B29C33/42 ,  B82Y30/00

    摘要： 본 발명은 베이스층 상에 하단보다 상단의 폭이 넓은 사다리꼴 형상의 마이크로 구조물이 형성되고, 마이크로 구조물의 상면을 선택적으로 식각함으로써, 마이크로 구조물의 상면을 이동하는 액적의 흐름속도를 제어할 수 있는 액적 흐름속도 제어표면의 제작방법 및 액적 흐름속도 제어표면에 관한 것이다. 이를 위하여, 본 발명은 액적 흐름속도 제어표면의 제작방법에 있어서, 일정간격 이격된 복수개의 음각 마이크로 라인구조가 형성된 고분자몰드를 제작하는 몰드 제작단계와, 상기 고분자몰드에 레플리카 공정을 수행하여, 일정간격 이격된 복수개의 마이크로 구조물이 형성된 구조체표면을 제작하는 표면 제작단계와, 상기 마이크로 구조물의 상면을 식각하여, 상기 마이크로 구조물의 상면에 나노 범프를 형성하는 식각단계를 포함하는 것을 특징으로 하는 액적 흐름속도 제어표면의 제작방법을 제공한다.

    LOW VOLTAGE CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER
    7.
    发明申请
    LOW VOLTAGE CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER 审中-公开

    公开(公告)号：WO2023047417A1

    公开(公告)日：2023-03-30

    申请号：PCT/IN2022/050851

    申请日：2022-09-23

    申请人： SENSONICS DEVICES PVT LTD

    发明人： PANWAR, . Brishbhan Singh ,  GUPTA, Rajat

    IPC分类号： H01L27/04 ,  B81C1/00 ,  B81B7/00 ,  H04R19/00

    摘要： A method for designing a low voltage capacitive micromachined ultrasonic transducer (CMUT) is provided. The method includes starting from a base silicon wafer includes starting with a N-type Silicon Wafer and growing base oxide by patterning with a metal mask over the base oxide, patterning with a Field Oxide (FOX) Mask over a copper (Cu) or Aluminium (Al) metal (M1) layer that is deposited over the base oxide, depositing polysilicon over the entire silicon wafer and doping the polysilicon with a donor species with a concentration approaching its respective solid solubility limit and subsequently depositing titanium (Ti) over the doped polysilicon that is deposited on the entire silicon wafer and subsequently depositing a dielectric layer. The dielectric layer is standalone Silicon Dioxide or in a stack with Hafnium Oxide or alternatively in a stack with Silicon Nitride or a suitable stack of high relative permittivity materials.

    VERBINDUNG EINES SENSORCHIPS MIT EINEM MESSOBJEKT
    8.
    发明申请
    VERBINDUNG EINES SENSORCHIPS MIT EINEM MESSOBJEKT 审中-公开

    公开(公告)号：WO2023016807A1

    公开(公告)日：2023-02-16

    申请号：PCT/EP2022/071079

    申请日：2022-07-27

    申请人： ZF FRIEDRICHSHAFEN AG

    发明人： LANG, Philipp ,  SCHWAB, Michael ,  SCHREIBMÜLLER, Nicolas

    IPC分类号： H01L23/00 ,  B81C1/00 ,  G01L19/00 ,  G01L19/14

    摘要： Die Erfindung betrifft ein Verfahren zur Verbindung eines Sensorchips (1) mit einem Messobjekt (2). Ein erster Verfahrensschritt (100) umfasst ein Auftragen von Silberpartikeln (11) auf einem Sensorchip (1), der dazu eingerichtet ist, eine physikalische Eigenschaft des Messobjekts (2) zu erfassen. In einem zweiten Verfahrensschritt (200) wird der Sensorchip (1) an dem Messobjekt (2) angeordnet, sodass sich die Silberpartikel (11) zwischen dem Sensorchip (1) und dem Messobjekt (2) befinden. In einem dritten Verfahrensschritt (300) erfolgt ein Erhitzen der Silberpartikel (11), sodass sich die Silberpartikel (11) durch Diffusionsprozesse zu einer Schicht (13) verbinden, welche nach ihrer Aushärtung den Sensorchip (1) stoffschlüssig mit dem Messobjekt (2) verbindet.

    SILICON MICRONEEDLE STRUCTURE AND PRODUCTION METHOD
    9.
    发明申请
    SILICON MICRONEEDLE STRUCTURE AND PRODUCTION METHOD 审中-公开

    公开(公告)号：WO2023007362A1

    公开(公告)日：2023-02-02

    申请号：PCT/IB2022/056870

    申请日：2022-07-26

    申请人： NANOPASS TECHNOLOGIES LTD.

    发明人： ADMATI, Gal ,  LEVIN, Yotam

    IPC分类号： A61M37/00 ,  B81C1/00

    摘要： A microneedle structure has one or more microneedles (104) projecting from the major surface (102) of a substrate (100). The microneedle has a penetrating tip (106) formed at an intersection between upright surfaces (108) and an inclined surface (110) corresponding to a (111) crystallographic plane. The microneedle has an expanding portion bounded by a continuation of the upright surfaces (108) and inclined surface (110), and a constant cross-section portion bounded by a continuation of the upright surfaces and a slicing plane (112) extending from an edge (114) of inclined surface (110) towards, and perpendicular to, major surface (102) of the substrate. A width W of inclined surface (110) increases monotonically from penetrating tip (106) to edge (114).

    USE OF TIN THIN FILM FOR BONDING AND AS MASKING FILM
    10.
    发明申请
    USE OF TIN THIN FILM FOR BONDING AND AS MASKING FILM 审中-公开

    公开(公告)号：WO2023280676A1

    公开(公告)日：2023-01-12

    申请号：PCT/EP2022/068101

    申请日：2022-06-30

    申请人： UNIVERSITY OF SOUTH-EASTERN NORWAY

    发明人： ROY, Avisek ,  BARDALEN, Eivind ,  ØHLCKERS, Per Alfred

    IPC分类号： B81C1/00 ,  H01L23/10

    摘要： The present invention relates to a method for micromachining a silicon structure especially for SLID bonding, comprising the steps of preparing a silicon wafer with a metal pattern on said silicon, said silicon being exposed outside said pattern, the metal pattern at least having an upper surface constisting of Sn. The method comprising a step of DRIE etching of the structure for etching cavities in said exposed silicon wafer essentially without etching said Sn top layer. The method also relates to the use of Sn as an etching mask in micromachining av silicon structures.