Invention Application
WO2018048555A1 MINIMUM/MAXIMUM AND BITWISE AND/OR BASED COARSE STENCIL TEST
审中-公开
最小/最大和最大值和/或基于粗体的测试
- Patent Title: MINIMUM/MAXIMUM AND BITWISE AND/OR BASED COARSE STENCIL TEST
- Patent Title (中): 最小/最大和最大值和/或基于粗体的测试
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Application No.: PCT/US2017/045961Application Date: 2017-08-08
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Publication No.: WO2018048555A1Publication Date: 2018-03-15
- Inventor: TOTH, Robert M. , MUNKBERG, Carl Jacob , HASSELGREN, Jon N.
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: AGHEVLI, Ramin
- Priority: US15/260,570 20160909
- Main IPC: G06T1/20
- IPC: G06T1/20 ; G06T1/60
Abstract:
Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.
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