公开(公告)号：WO2018052512A3

公开(公告)日：2018-03-22

申请号：PCT/US2017/041441

申请日：2017-07-11

Applicant: INTEL CORPORATION

Inventor： AKENINE-MOLLER, Tomas G. ,  MUNKBERG, Carl J. ,  HASSELGREN, Jon N.

IPC: G06T1/20 ,  G06T1/60

Abstract: Briefly, in accordance with one or more embodiments, an architecture to load balance tessellation distribution apparatus comprises a memory to store one or more patches representing an object in an image, and a processor, coupled to the memory, to perform one or more tessellation operations on the one or more patches. The one or more tessellation operations including splitting one or more of the patches into one or more subpatches, and load balancing the one or more patches and the one or more subpatches among two or more geometry and setup fixed-function pipelines (GSPs).

公开(公告)号：WO2017095478A1

公开(公告)日：2017-06-08

申请号：PCT/US2016/043190

申请日：2016-07-20

Applicant: INTEL CORPORATION

Inventor： TOTH, Robert M. ,  HASSELGREN, Jon N.

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/54

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T2207/20021

Abstract: A mechanism is described for facilitating efficient processing of graphics data using triple buffered constant buffers at computing devices. A method of embodiments, as described herein, includes detecting generation of a multi-block buffer by an application to perform data processing at a graphics processor of a computing device, and mapping a first memory block of the multi-block buffer to the graphics processor, where mapping further includes mapping a second memory block and a third memory block of the multi-block buffer to an application processor. The method further includes executing a swap operation to facilitate the graphics processor to process a current data set associated with the application processor.

Abstract translation: 描述了一种机制，其用于在计算设备处使用三重缓冲常量缓冲器来有效地处理图形数据。 如本文所述的实施例的方法包括检测应用程序由应用程序生成多块缓冲器以在计算设备的图形处理器处执行数据处理，并且将多块缓冲器的第一存储器块映射到图形处理器 其中映射还包括将多块缓冲器的第二存储器块和第三存储器块映射到应用处理器。 该方法还包括执行交换操作以促进图形处理器处理与应用处理器相关联的当前数据集。

公开(公告)号：WO2016073125A1

公开(公告)日：2016-05-12

申请号：PCT/US2015/054340

申请日：2015-10-07

Applicant: INTEL CORPORATION

Inventor： AKENINE-MÖLLER, Tomas G. ,  HASSELGREN, Jon N. ,  MUNKBERG, Carl. J.

IPC: G06T15/00

CPC classification number: G06T15/40 ,  G06T11/40

Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.

Abstract translation: 根据一些实施例，零覆盖测试可以确定诸如三角形的原语是否依赖于行或列或样本行之间的通道。 如果是这样，可以在零覆盖率拣选测试中剔除原语。

公开(公告)号：WO2018052592A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/046546

申请日：2017-08-11

Applicant: INTEL CORPORATION

Inventor： ANDERSSON, Magnus ,  AKENINE-MOLLER, Tomas G. ,  HASSELGREN, Jon N.

IPC: G06T15/40 ,  G06T7/50 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/40 ,  G06T17/20

Abstract: An apparatus and method are described for performing an efficient depth prepass. For example, one embodiment of a method comprising: a method comprising: performing a first pass through a specified portion of a graphics pipeline with only depth rendering active; initializing a coarse depth buffer within the specified portion of the graphics pipeline during the first pass, the coarse depth buffer storing depth data at a level of granularity less than that stored in a per-pixel depth buffer, which is not initialized during the first pass; and performing a second pass through the graphics pipeline following the first pass, the second pass utilizing the full graphics pipeline and using values in the coarse depth buffer initialized by the first pass.

Abstract translation: 描述了用于执行有效深度准备的装置和方法。 例如，一种方法的一个实施例包括：一种方法，包括：在只有深度渲染活动的情况下执行第一遍通过图形管线的指定部分; 在第一遍期间初始化图形流水线的指定部分内的粗略深度缓冲器，粗略深度缓冲器以比在第一遍期间未初始化的每像素深度缓冲器中存储的粒度水平更低的粒度水平来存储深度数据 ; 以及在第一遍之后通过图形流水线执行第二遍，第二遍使用全图形流水线并且使用由第一遍初始化的粗略深度缓存器中的值。

公开(公告)号：WO2018048555A1

公开(公告)日：2018-03-15

申请号：PCT/US2017/045961

申请日：2017-08-08

Applicant: INTEL CORPORATION

Inventor： TOTH, Robert M. ,  MUNKBERG, Carl Jacob ,  HASSELGREN, Jon N.

IPC: G06T1/20 ,  G06T1/60

Abstract: Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.

Abstract translation: 描述与用于提供最小或最大以及按位逻辑AND或逻辑OR基粗略模板测试的技术有关的方法和设备。 在一个实施例中，元数据（对应于多个像素）被存储在存储器中。 对元数据执行一个或多个操作以生成模板结果。 该一个或多个操作包括逐位相交操作或逐位联合操作和/或最小操作或最大操作。 其他实施例也被公开和要求保护。

公开(公告)号：WO2017105612A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/057030

申请日：2016-10-14

Applicant: INTEL CORPORATION

Inventor： AKENINE-MOLLER, Tomas G. ,  HASSELGREN, Jon N. ,  NILSSON, Jim K.

IPC: H04N19/80 ,  H04N19/186 ,  H04N19/119 ,  H04N19/176 ,  H04N19/597 ,  H04N19/42

CPC classification number: G06T9/00 ,  G06T9/004 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80

Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.

Abstract translation: 描述了用于有助于在计算设备处有效处理图形数据的插值最小 - 最大压缩/解压缩的机制。 如本文所述的实施例的方法包括：检测具有表示能够由计算设备的图形处理器处理的图形内容的像素的图块; 计算瓦片的最小颜色值和最大颜色值。 该方法可以进一步包括将瓦片分成多个内插瓦片，其中每个内插瓦片包括一组一个或多个颜色的像素。 该方法可以进一步包括计算多个内插瓦片的多个局部最小颜色值，基于多个局部最小值计算多个内插瓦片的多个残差，以减少来自多个内插瓦片的扩展 ，并且基于所述多个残差来压缩所述缩减的多个内插瓦片。

公开(公告)号：WO2012149084A3

公开(公告)日：2012-11-01

申请号：PCT/US2012/035084

申请日：2012-04-26

Applicant: INTEL CORPORATION ,  ANDERSSON, Magnus ,  AKENINE-MÖLLER, Thomas G. ,  HASSELGREN, Jon N.

Inventor： ANDERSSON, Magnus ,  AKENINE-MÖLLER, Thomas G. ,  HASSELGREN, Jon N.

IPC: G06T9/00 ,  G06T15/00

Abstract: A depth buffer compression scheme uses bilinear patches as a predictor for depth. The scheme targets compression of scenes rendered with stochastic blur rasterization. A tile of fragments may be split into two or more regions and a higher-degree function may be fit to each region. The residuals are then stored as delta corrections.

公开(公告)号：WO2012047681A2

公开(公告)日：2012-04-12

申请号：PCT/US2011/053549

申请日：2011-09-27

Applicant: INTEL CORPORATION ,  JOHNSSON, Bjorn ,  CLARBERG, Franz P. ,  ANDERSSON, Magnus ,  HASSELGREN, Jon N. ,  AKENINE-MOLLER, Tomas ,  MUNKBERG, Carl J

Inventor： JOHNSSON, Bjorn ,  ANDERSSON, Magnus ,  HASSELGREN, Jon N. ,  AKENINE-MOLLER, Tomas ,  MUNKBERG, Carl J

IPC: G06T15/06 ,  G06T9/20 ,  G06T15/80

CPC classification number: G06T15/06 ,  H04N13/275 ,  H04N13/282

Abstract: A multi-view image may be generated by detecting discontinuities in a radiance function using multi-view silhouette edges. A multi-view silhouette edge is an edge of a triangle that intersects a back tracing plane and, in addition, the triangle faces backwards, as seen from the intersection point, and the edge is not further connected to any back facing triangles. Analytical visibility may be computed between shading points and a camera line and shared shading computations may be reused.

Abstract translation: 可以通过使用多视图轮廓边检测辐射函数中的不连续性来生成多视图图像。 多视角轮廓边是三角形的边，与相交的后面跟踪平面相交，另外，从相交点看，三角形面朝后，并且边不再与任何背面三角形相连。 可以在阴影点和相机线之间计算分析可见度，共享阴影计算可以重复使用。

公开(公告)号：WO2017204948A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/028454

申请日：2017-04-19

Applicant: INTEL CORPORATION

Inventor： AKENINE-MOLLER, Tomas G. ,  ANDERSSON, Magnus ,  HASSELGREN, Jon N. ,  SEILER, Larry

IPC: G06T15/40 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T15/005 ,  G06T2210/12

Abstract: An apparatus and method are described for occlusion queries for accelerated rendering. For example, one embodiment of a method comprises: performing an occlusion query for a plurality of tiles of an image, the occlusion query to determine whether one or more of the tiles are occluded; generating a bit mask in response to the occlusion query, the bit mask comprising data indicating which of the tiles are occluded; and reading the bit mask when rendering the image to remove work associated with those tiles which are occluded.

Abstract translation: 描述了用于加速渲染的遮挡查询的装置和方法。 例如，方法的一个实施例包括：对图像的多个图块执行遮挡查询，遮挡查询确定一个或多个图块是否被遮挡; 响应于所述遮挡查询生成位掩码，所述位掩码包括指示哪些所述瓦片被遮挡的数据; 并在渲染图像时读取位掩码以消除与被遮挡的图块关联的工作。

公开(公告)号：WO2015171310A1

公开(公告)日：2015-11-12

申请号：PCT/US2015/026996

申请日：2015-04-22

Applicant: INTEL CORPORATION

Inventor： AKENINE-MÖLLER, Tomas G. ,  HASSELGREN, Jon N. ,  MUNKBERG, Carl. J.

IPC: G06T1/60 ,  G06T9/00 ,  G06T15/00 ,  H04N19/186

CPC classification number: H04N19/136 ,  G06T9/00 ,  G06T11/00 ,  G06T11/40 ,  H04N1/41 ,  H04N19/137 ,  H04N19/186 ,  H04N19/428 ,  H04N19/50

Abstract: First, the colors are partitioned within a tile into distinct groups, such that the variation of color within each group is lowered. Second, each group can be encoded in an efficient manner. The algorithm described herein may give a higher compression ratio than previous algorithms, and therefore may further reduce memory bandwidth at a very low increase in computational cost in some embodiments. The algorithm may be added to a system with existing buffer compression algorithms, handling additional tiles that the existing algorithm fails to compress, thereby increasing the overall compression rate.

Abstract translation: 首先，将颜色在瓦片内划分成不同的组，使得每组中的颜色变化降低。 第二，每组可以有效地编码。 这里描述的算法可以给出比先前的算法更高的压缩比，并且因此在一些实施例中可以以非常低的计算成本增加进一步减少存储器带宽。 可以将该算法添加到具有现有缓冲器压缩算法的系统中，处理现有算法无法压缩的附加瓦片，从而增加总体压缩率。