Invention Application
- Patent Title: RESISTOR BETWEEN GATES IN SELF-ALIGNED GATE EDGE ARCHITECTURE
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Application No.: PCT/US2017/025589Application Date: 2017-03-31
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Publication No.: WO2018182736A1Publication Date: 2018-10-04
- Inventor: OLAC-VAW, Roman W. , HAFEZ, Walid M. , JAN, Chia-Hong , CHANG, Hsu-Yu , DIAS, Neville L. , RAMASWAMY, Rahul , NIDHI, Nidhi , LEE, Chen-Guan
- Applicant: INTEL CORPORATION
- Applicant Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: 2200 Mission College Boulevard Santa Clara, California 95054 US
- Agency: ABRAHAM, Ion C.
- Main IPC: H01L27/07
- IPC: H01L27/07 ; H01L29/66
Abstract:
Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
Information query
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