公开(公告)号：WO2018118087A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068580

申请日：2016-12-23

Applicant: INTEL CORPORATION

Inventor： BAMBERY, Rohan K. ,  HAFEZ, Walid M. ,  WU, Mong-Kai

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L21/823821 ,  H01L23/5256 ,  H01L27/0924

Abstract: Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure.

公开(公告)号：WO2018063259A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054543

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： HAFEZ, Walid M. ,  OLAC-VAW, Roman W. ,  PARK, Joodong ,  LEE, Chen-Guan ,  JAN, Chia-Hong

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

Abstract translation: 描述了具有金属电阻器的金属电阻器和自对准栅极边缘（SAGE）架构。 在一个示例中，半导体结构包括通过衬底上方的沟槽隔离区域突出的多个半导体鳍。 第一栅极结构位于多个半导体鳍中的第一个之上。 第二栅极结构位于多个半导体鳍中的第二个之上。 栅极边缘隔离结构横向地位于第一栅极结构和第二栅极结构之间并与其接触。 栅极边缘隔离结构位于沟槽隔离区域上并且延伸到第一栅极结构和第二栅极结构的最上表面之上。 金属层位于栅极边缘隔离结构上，并与第一栅极结构和第二栅极结构电隔离。

公开(公告)号：WO2018004528A1

公开(公告)日：2018-01-04

申请号：PCT/US2016/039749

申请日：2016-06-28

Applicant: INTEL CORPORATION

Inventor： LIN, Jui-Yen ,  LEE, Chen-Guan ,  PARK, Joodong ,  HAFEZ, Walid M. ,  SHIH, Kun-Huan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/2815 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6656

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

Abstract translation: 一个实施例包括一种装置，该装置包括：晶体管，其包括具有第一和第二侧壁的源极，漏极和栅极; 在漏极和栅极之间的第一侧壁上的第一隔离物; 在源极和栅极之间的第二侧壁上的第二隔离物; 以及第一间隔物上的第三间隔物。 这里描述了其他实施例。

公开(公告)号：WO2016010515A1

公开(公告)日：2016-01-21

申请号：PCT/US2014/046525

申请日：2014-07-14

Applicant: INTEL CORPORATION

Inventor： HAFEZ, Walid M. ,  JAN, Chia-Hong

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

Abstract translation: 对于基于鳍的电子器件描述了固体源极扩散结。 在一个示例中，在基板上形成翅片。 第一掺杂剂类型的玻璃沉积在衬底上并且在鳍的下部上方。 在衬底和鳍上沉积一层第二掺杂剂类型。 将玻璃退火以将掺杂剂驱动到翅片和基底中。 去除玻璃并且在翅片之上形成第一和第二接触件，而不接触翅片的下部。

公开(公告)号：WO2015047313A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062308

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  OLAC-VAW, Roman W. ,  HAFEZ, Walid M. ,  JAN, Chia-Hong ,  LIU, Pei-Chi

Inventor： OLAC-VAW, Roman W. ,  HAFEZ, Walid M. ,  JAN, Chia-Hong ,  LIU, Pei-Chi

IPC: H01L27/00

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract translation: 描述了在公共基板上具有不同功函数的非平面I / O和逻辑半导体器件以及在公共基板上制造具有不同功函数的非平面I / O和逻辑半导体器件的方法。 例如，半导体结构包括设置在基板上方的第一半导体器件。 第一半导体器件具有导电类型，并且包括具有第一功函数的栅电极。 半导体结构还包括设置在基板上方的第二半导体器件。 第二半导体器件具有导电类型，并且包括具有第二不同功函数的栅电极。

公开(公告)号：WO2014209284A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/047622

申请日：2013-06-25

Applicant: INTEL CORPORATION

Inventor： CHANG, Ting ,  JAN, Chia-Hong ,  HAFEZ, Walid M.

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11563 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer.

Abstract translation: 描述了具有隔离电荷位置的存储单元和制造具有隔离电荷位点的存储单元的方法。 在一个示例中，非易失性电荷陷阱存储器件包括具有沟道区，源极区和漏极区的衬底。 栅极堆叠设置在衬底上方，在沟道区域上方。 栅堆叠包括设置在沟道区上方的隧道介电层，第一电荷俘获区和第二电荷捕获区。 这些区域设置在隧道介电层上方并分开一段距离。 栅堆叠还包括设置在隧道介电层上方和第一电荷俘获区与第二电荷俘获区之间的隔离电介质层。 栅电介质层设置在第一电荷捕获区，第二电荷捕获区和隔离电介质层的上方。 栅电极设置在栅介质层上。

公开(公告)号：WO2018203887A1

公开(公告)日：2018-11-08

申请号：PCT/US2017/030725

申请日：2017-05-03

Applicant: INTEL CORPORATION

Inventor： LIU, En-Shao ,  CASSIDY-COMFORT, Everett Steven ,  PARK, Joodong ,  HAFEZ, Walid M. ,  LIN, Jui-Yen ,  NIDHI, Nidhi ,  LEE, Chen-Guan ,  JAN, Chia-Hong

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

Abstract: Disclosed herein are vertical capacitors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, a vertical capacitor may include at least two conductive plates on a support, with the conductive plates spaced apart by a dielectric material on the support.

公开(公告)号：WO2018111226A1

公开(公告)日：2018-06-21

申请号：PCT/US2016/066232

申请日：2016-12-12

Applicant: INTEL CORPORATION

Inventor： LEE, Chen-guan ,  CHANG, Hsu-yu ,  PARK, Joodong ,  HAFEZ, Walid M. ,  JAN, Chia-hong

IPC: H01L29/78 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a transistor including a drain, a source, and a channel between the drain and the source. The channel may include a first channel portion and a second channel portion adjacent to the first channel portion. The transistor may include a gate, wherein the gate may include a first gate portion and a second gate portion, where the first gate portion may include a first metal, and the second gate portion may include a second metal different from the first metal. The first gate portion may overlap the first channel portion, and the first gate portion and the second gate portion may overlap the second channel portion.

公开(公告)号：WO2018063366A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054899

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： HAFEZ, Walid M. ,  OLAC-VAW, Roman W. ,  PARK, Joodong ,  LEE, Chen-Guan ,  JAN, Chia-Hong ,  CASSIDY-COMFORT, Everett S.

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/28

Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.

Abstract translation: 描述了具有双栅极电介质的超缩放翅片间距工艺。 例如，半导体结构包括衬底之上的第一和第二半导体鳍。 第一栅极结构包括在顶表面上方且与第一半导体鳍状物的侧壁横向相邻的第一栅电极，在第一栅电极与第一半导体鳍状物之间并且沿着第一栅极结构的侧壁的第一栅电介质层， 在所述第一栅极电极和所述第一栅极电介质层之间以及沿着所述第一栅极电极的侧壁沿着所述第一栅极电介质层的第二栅极电介质层。 第二栅极结构包括在顶表面之上且与第二半导体鳍状物的侧壁横向相邻的第二栅电极以及在第二栅电极与第二半导体鳍之间以及沿着第二栅电极的侧壁的第二栅电介质层。 / p>

公开(公告)号：WO2015199709A1

公开(公告)日：2015-12-30

申请号：PCT/US2014/044479

申请日：2014-06-27

Applicant: INTEL CORPORATION

Inventor： DIAS, Neville L. ,  JAN, Chia-Hong ,  HAFEZ, Walid M. ,  OLAC-VAW, Roman W. ,  CHANG, Hsu-Yu ,  CHANG, Ting ,  RAMASWAMY, Rahul ,  LIU, Pei-Chi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7853 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

Abstract translation: 一个实施例包括一种设备，包括：非平面翅片，其具有第一，第二和第三部分，每个部分具有主轴和短轴，并且每个彼此是整体的; 其中（a）第一，第二和第三部分的长轴彼此平行，（b）第一和第二部分的长轴彼此不共线，（c）第一， 第二和第三部分包括从包括源极，漏极和沟道的组中选择的晶体管的节点，（e）第一，第二和第三部分包括至少一个finFET。 本文描述了其它实施例。