公开(公告)号：WO2018063366A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054899

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： HAFEZ, Walid M. ,  OLAC-VAW, Roman W. ,  PARK, Joodong ,  LEE, Chen-Guan ,  JAN, Chia-Hong ,  CASSIDY-COMFORT, Everett S.

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/28

Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.

Abstract translation: 描述了具有双栅极电介质的超缩放翅片间距工艺。 例如，半导体结构包括衬底之上的第一和第二半导体鳍。 第一栅极结构包括在顶表面上方且与第一半导体鳍状物的侧壁横向相邻的第一栅电极，在第一栅电极与第一半导体鳍状物之间并且沿着第一栅极结构的侧壁的第一栅电介质层， 在所述第一栅极电极和所述第一栅极电介质层之间以及沿着所述第一栅极电极的侧壁沿着所述第一栅极电介质层的第二栅极电介质层。 第二栅极结构包括在顶表面之上且与第二半导体鳍状物的侧壁横向相邻的第二栅电极以及在第二栅电极与第二半导体鳍之间以及沿着第二栅电极的侧壁的第二栅电介质层。 / p>

公开(公告)号：WO2015199709A1

公开(公告)日：2015-12-30

申请号：PCT/US2014/044479

申请日：2014-06-27

Applicant: INTEL CORPORATION

Inventor： DIAS, Neville L. ,  JAN, Chia-Hong ,  HAFEZ, Walid M. ,  OLAC-VAW, Roman W. ,  CHANG, Hsu-Yu ,  CHANG, Ting ,  RAMASWAMY, Rahul ,  LIU, Pei-Chi

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7853 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

Abstract translation: 一个实施例包括一种设备，包括：非平面翅片，其具有第一，第二和第三部分，每个部分具有主轴和短轴，并且每个彼此是整体的; 其中（a）第一，第二和第三部分的长轴彼此平行，（b）第一和第二部分的长轴彼此不共线，（c）第一， 第二和第三部分包括从包括源极，漏极和沟道的组中选择的晶体管的节点，（e）第一，第二和第三部分包括至少一个finFET。 本文描述了其它实施例。

公开(公告)号：WO2018182733A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025582

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： OLAC-VAW, Roman W. ,  HAFEZ, Walid M. ,  JAN, Chia-Hong ,  NIDHI, Nidhi

IPC: H01L27/07 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed on the first structure, the second structure extending at least between the first gate structure and the second gate structure.

公开(公告)号：WO2018111243A1

公开(公告)日：2018-06-21

申请号：PCT/US2016/066385

申请日：2016-12-13

Applicant: INTEL CORPORATION

Inventor： RAMASWAMY, Rahul ,  CHANG, Hsu-Yu ,  JAN, Chia-Hong ,  HAFEZ, Walid M. ,  DIAS, Neville L. ,  OLAC-VAW, Roman W. ,  LEE, Chen-Guan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/02236 ,  H01L21/02241 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

公开(公告)号：WO2018075072A1

公开(公告)日：2018-04-26

申请号：PCT/US2016/058259

申请日：2016-10-21

Applicant: INTEL CORPORATION

Inventor： JAN, Chia-Hong ,  HAFEZ, Walid M. ,  DIAS, Neville L. ,  RAMASWAMY, Rahul ,  CHANG, Hsu-Yu ,  OLAC-VAW, Roman W. ,  LEE, Chen-Guan

IPC: H01L27/08 ,  H01L21/768

CPC classification number: H01L28/24 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/30608 ,  H01L27/0629

Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode or cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.

Abstract translation: 描述了基于鳍片的薄膜电阻器以及制造鳍片型薄膜电阻器的方法。 在一个示例中，集成电路结构包括突出穿过衬底上方的沟槽隔离区的鳍。 鳍包括半导体材料并且具有顶表面，第一端，第二端以及在第一端和第二端之间的一对侧壁。 隔离层与鳍的顶表面，第一端，第二端和一对侧壁共形。 电阻层与隔离层共形，所述隔离层与鳍的顶表面，第一端，第二端和一对侧壁共形。 第一阳极或阴极电极电连接到电阻器层。 第二阳极或阴极电极电连接到电阻层。

公开(公告)号：WO2018063394A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055004

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： JAN, Chia-Hong ,  HAFEZ, Walid M. ,  CHANG, Hsu-Yu ,  DIAS, Neville L. ,  RAMASWAMY, Rahul ,  OLAC-VAW, Roman W. ,  LEE, Chen-Guan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

Abstract translation: 一种晶体管器件，包括晶体管，所述晶体管包括设置在衬底上的本体，接触所述本体的至少两个相邻侧以及所述栅极叠层的相对侧上的源极和漏极的栅极叠层以及沟道 限定在源极和漏极之间的本体中，其中沟道的导电性与源极和漏极的导电性相似。 描述包括耦合到逻辑电路的驱动器电路的输入/输出（IO）电路，所述驱动器电路包括至少一个晶体管器件。 一种方法，包括：在包括导电性的衬底上形成晶体管器件的沟道; 在沟道的相对侧上形成源极和漏极，其中源极和漏极包括与沟道相同的导电性; 并在通道上形成栅极叠层。

公开(公告)号：WO2018182736A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025589

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： OLAC-VAW, Roman W. ,  HAFEZ, Walid M. ,  JAN, Chia-Hong ,  CHANG, Hsu-Yu ,  DIAS, Neville L. ,  RAMASWAMY, Rahul ,  NIDHI, Nidhi ,  LEE, Chen-Guan

IPC: H01L27/07 ,  H01L29/66

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

公开(公告)号：WO2018111223A1

公开(公告)日：2018-06-21

申请号：PCT/US2016/066224

申请日：2016-12-12

Applicant: INTEL CORPORATION

Inventor： JAN, Chia-Hong ,  HAFEZ, Walid M. ,  DIAS, Neville L. ,  RAMASWAMY, Rahul ,  CHANG, Hsu-Yu ,  OLAC-VAW, Roman W. ,  LEE, Chen-Guan

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66 ,  H01L29/66356 ,  H01L29/66818 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

公开(公告)号：WO2018063365A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054896

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： HAFEZ, Walid M. ,  OLAC-VAW, Roman W. ,  JAN, Chia-Hong

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06

Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.

Abstract translation: 描述了用于自对准门极边缘体系结构的双鳍端盖以及制造用于自对准门极边缘体系结构的双鳍端盖的方法。 在一个示例中，半导体结构包括具有第一多个半导体鳍的I / O器件，所述第一多个半导体鳍设置在衬底之上并且突出穿过沟槽隔离层的最上表面。 具有第二多个半导体鳍的逻辑器件设置在衬底上方并且突出穿过沟槽隔离层的最上表面。 在I / O设备和逻辑器件之间设置栅极边缘隔离结构。 最靠近栅极边缘隔离结构的第一多个半导体鳍的半导体鳍与栅极边缘隔离结构相比距离栅极边缘隔离结构最近的第二多个半导体鳍的半导体鳍远离栅极边缘隔离结构。

公开(公告)号：WO2018125226A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069538

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： RAMASWAMY, Rahul ,  JAN, Chia-Hong ,  HAFEZ, Walid ,  DIAS, Neville ,  CHANG, Hsu-Yu ,  OLAC-VAW, Roman W. ,  LEE, Chen-Guan

IPC: H01P3/12 ,  H01P3/123

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.