VIA PLACEMENT FOR SLIM BORDER ELECTRO-OPTIC DISPLAY BACKPLANES WITH DECREASED CAPACITIVE COUPLING BETWEEN T-WIRES AND PIXEL ELECTRODES
Abstract:
An electro-optic display including an array of pixel electrodes, where each row of pixel electrodes is associated with a source line, and that source line is connected to a drive chip with a T-wire that connects from the back of the substrate to the front of the substrate through a via. The vias are spaced out, such as in a zig-zag pattern or a pseudo-random pattern to reduce the capacitive coupling between the T-wires when adjacent pixels are driven, for example when presenting text characters.
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