Invention Application
- Patent Title: VIA PLACEMENT FOR SLIM BORDER ELECTRO-OPTIC DISPLAY BACKPLANES WITH DECREASED CAPACITIVE COUPLING BETWEEN T-WIRES AND PIXEL ELECTRODES
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Application No.: PCT/US2019/017592Application Date: 2019-02-12
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Publication No.: WO2019160841A1Publication Date: 2019-08-22
- Inventor: HO, Chih-Hsiang , LU, Yi , BEN-DOV, Yuval , SIM, Teck Ping
- Applicant: E INK CORPORATION
- Applicant Address: Attn: IP Department 1000 Technology Park Drive Billerica, Massachusetts 01821-4165 US
- Assignee: E INK CORPORATION
- Current Assignee: E INK CORPORATION
- Current Assignee Address: Attn: IP Department 1000 Technology Park Drive Billerica, Massachusetts 01821-4165 US
- Agency: BEAN, Brian
- Priority: US62/631,261 20180215
- Main IPC: G02F1/1685
- IPC: G02F1/1685 ; G02F1/167 ; G02F1/1676
Abstract:
An electro-optic display including an array of pixel electrodes, where each row of pixel electrodes is associated with a source line, and that source line is connected to a drive chip with a T-wire that connects from the back of the substrate to the front of the substrate through a via. The vias are spaced out, such as in a zig-zag pattern or a pseudo-random pattern to reduce the capacitive coupling between the T-wires when adjacent pixels are driven, for example when presenting text characters.
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