A technique of producing a device comprising a stack of layers defining an array of transistors and including one or more electrically conductive interlayer connections, wherein the method comprises: forming a source-drain conductor pattern defining an array of source conductors each providing an addressing line for a respective set of transistors of the transistor array, and an array of drain conductors each associated with a respective transistor of the transistor array; wherein forming said source-drain conductor pattern comprises forming a first conductor subpattern and thereafter forming a second conductor subpattern, wherein said first conductor subpattern provides the conductive surface of the source-drain conductor pattern in one or more interconnect regions where electrically conductive interlayer connections are to be formed to the source-drain conductor pattern, and the second conductor subpattern provides the conductive surface of the source-drain conductor pattern at least in the regions where the source and drain conductors are in closest proximity.