公开(公告)号：WO2019229256A1

公开(公告)日：2019-12-05

申请号：PCT/EP2019/064223

申请日：2019-05-31

Applicant: FLEXENABLE LIMITED

Inventor： SOCRATOUS, Josephine ,  VANDEKERCHOVE, Herve

IPC: H01L27/12 ,  H01L51/10 ,  H01L27/28

Abstract: A technique of producing a device comprising a stack of layers defining an array of transistors and including one or more electrically conductive connections between levels, wherein the method comprises: forming a source-drain conductor pattern defining an array of source conductors each providing an addressing line for a respective set of transistors of the transistor array, and an array of drain conductors each associated with a respective transistor of the transistor array; wherein forming said source-drain conductor pattern comprises: forming a first conductor subpattern which comprises conductor material at least in the regions of the addressing lines and provides the conductive surface of the source-drain conductor pattern at least in the regions where the source and drain conductors are in closest proximity; masking the first conductor subpattern in regions where the source and drain conductors are in closest proximity; thereafter forming a second conductor subpattern, which also comprises conductor material at least in the regions of the addressing lines and which provides the conductive surface of the source-drain conductor pattern in one or more interconnect regions where electrically conductive interlayer connections are to be formed to the source-drain conductor pattern; thereafter de-masking the first conductor subpattern in the regions where the source and drain conductors are in closest proximity; and patterning a layer of semiconductor channel material in situ over the source-drain conductor pattern.

公开(公告)号：WO2019229254A1

公开(公告)日：2019-12-05

申请号：PCT/EP2019/064220

申请日：2019-05-31

Applicant: FLEXENABLE LIMITED

Inventor： SOCRATOUS, Josephine ,  VANDEKERCHOVE, Herve

IPC: H01L51/00 ,  H01L27/28 ,  H01L27/32 ,  H01L27/12

Abstract: A technique of producing a device comprising a stack of layers defining an array of transistors and including one or more electrically conductive interlayer connections, wherein the method comprises: forming a source-drain conductor pattern defining an array of source conductors each providing an addressing line for a respective set of transistors of the transistor array, and an array of drain conductors each associated with a respective transistor of the transistor array; wherein forming said source-drain conductor pattern comprises forming a first conductor subpattern and thereafter forming a second conductor subpattern, wherein said first conductor subpattern provides the conductive surface of the source-drain conductor pattern in one or more interconnect regions where electrically conductive interlayer connections are to be formed to the source-drain conductor pattern, and the second conductor subpattern provides the conductive surface of the source-drain conductor pattern at least in the regions where the source and drain conductors are in closest proximity.