Invention Application
- Patent Title: ERROR CORRECTION BIT FLIPPING SCHEME
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Application No.: PCT/US2019/058141Application Date: 2019-10-25
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Publication No.: WO2020112285A1Publication Date: 2020-06-04
- Inventor: KWAK, Jongtae
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: 8000 S. Federal Way Boise, Idaho 83716-9632 US
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: 8000 S. Federal Way Boise, Idaho 83716-9632 US
- Agency: HARRIS, Philip
- Priority: US16/199,773 20181126
- Main IPC: G11C29/52
- IPC: G11C29/52 ; G06F11/10 ; H03M13/11
Abstract:
Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
Information query