公开(公告)号：WO2009154906A2

公开(公告)日：2009-12-23

申请号：PCT/US2009/044003

申请日：2009-05-14

Applicant: MICRON TECHNOLOGY, INC. ,  KWAK, Jongtae

Inventor： KWAK, Jongtae

IPC: G11C11/4076 ,  G11C8/00 ,  H03K5/15 ,  G06F1/06 ,  G11C7/00

CPC classification number: H03L7/0814 ,  H03L7/0805

Abstract: An apparatus and method for multi -phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals (A, B) delayed from first edges of a clock signal (CLK) having a first frequency. Each of the first and second intermediate signals (A, B) has a second frequency that is half of the first frequency. The first and second intermediate signals {A, B) have a phase difference of 180° from each other. The apparatus also includes a first delay line (410a) delaying the first intermediate signal (A) by a first delay amount; a second delay line (410b) delaying the first intermediate signal (A) by a second delay amount; a third delay line (410c) delaying the second intermediate signal (B) by a third delay amount; and a fourth delay line (410d) delaying the second intermediate signal (B) by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.

Abstract translation: 公开了一种用于多相时钟生成的装置和方法。 该装置的一个实施例包括产生从具有第一频率的时钟信号（CLK）的第一边缘延迟的第一和第二中间信号（A，B）的模块。 第一和第二中间信号（A，B）中的每一个具有作为第一频率的一半的第二频率。 第一和第二中间信号{A，B）的相位差彼此相差180°。 该装置还包括延迟第一中间信号（A）第一延迟量的第一延迟线（410a） 第二延迟线（410b）将所述第一中间信号（A）延迟第二延迟量; 第三延迟线（410c）将所述第二中间信号（B）延迟第三延迟量; 以及第四延迟线（410d），将第二中间信号（B）延迟第四延迟量。 该装置还包括用于检测和调整第二和第四延迟量的闭合反馈回路。

公开(公告)号：WO2018160499A1

公开(公告)日：2018-09-07

申请号：PCT/US2018/019781

申请日：2018-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LEE, Hyun Yoo ,  KWAK, Jongtae ,  TATAPUDI, Suryanarayana

IPC: G11C7/22

Abstract: Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories are disclosed. In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：WO2021252163A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/033457

申请日：2021-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YAMAMOTO, Nobuo ,  MORGAN, Donald, Martin ,  WONG, Victor ,  KWAK, Jongtae

IPC: G11C11/22 ,  G06F11/10 ,  G11C11/221 ,  G11C11/401 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

公开(公告)号：WO2020112285A1

公开(公告)日：2020-06-04

申请号：PCT/US2019/058141

申请日：2019-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KWAK, Jongtae

IPC: G11C29/52 ,  G06F11/10 ,  H03M13/11

Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).

公开(公告)号：WO2020180804A1

公开(公告)日：2020-09-10

申请号：PCT/US2020/020679

申请日：2020-03-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SCHAEFER, Scott, E. ,  KWAK, Jongtae ,  BOEHM, Aaron, P.

IPC: G06F11/10 ,  G11C29/38 ,  G06F3/06

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：WO2020055731A1

公开(公告)日：2020-03-19

申请号：PCT/US2019/050177

申请日：2019-09-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： RIHO, Yoshiro ,  SHIMIZU, Atsushi ,  PARK, Sang-Kyun ,  KWAK, Jongtae

IPC: G06F11/10 ,  G06F13/16 ,  H03M13/31

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

公开(公告)号：WO2015160569A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/024694

申请日：2015-04-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HADRICK, Mark K. ,  WRIGHT, Jeffrey P. ,  WONG, Victor ,  LOVETT, Simon J. ,  MORGAN, Donald M. ,  JONES, William F. ,  AYYAPUREDDI, Sujeet ,  GANS, Dean D. ,  KWAK, Jongtae

IPC: G11C8/06 ,  G11C8/10

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 在其中。