Invention Application
- Patent Title: THREE-DIMENSIONAL NOR ARRAY INCLUDING VERTICAL WORD LINES AND DISCRETE CHANNELS AND METHODS OF MAKING THE SAME
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Application No.: PCT/US2020/025933Application Date: 2020-03-31
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Publication No.: WO2021133427A1Publication Date: 2021-07-01
- Inventor: RAJASHEKHAR, Adarsh , ZHOU, Fei , MAKALA, Raghuveer S. , ZHANG, Yanli , SHARANGPANI, Rahul
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: 5080 Spectrum Drive
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: 5080 Spectrum Drive
- Agency: RADOMSKY, Leon et al.
- Priority: US16/728,825 2019-12-27
- Main IPC: H01L27/1158
- IPC: H01L27/1158 ; H01L27/11568 ; H01L27/11521 ; H01L27/11553 ; H01L29/792 ; H01L29/788 ; H01L29/66 ; H01L21/768 ; H01L27/11556 ; H01L27/11582 ; H01L27/11597 ; H01L29/41741
Abstract:
A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.
Information query
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