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    MULTI-TIER MEMORY STACK STRUCTURE CONTAINING TWO TYPES OF SUPPORT PILLAR STRUCTURES
    3.
    发明申请
    MULTI-TIER MEMORY STACK STRUCTURE CONTAINING TWO TYPES OF SUPPORT PILLAR STRUCTURES 审中-公开
    含有两种支撑柱结构的多层存储器堆栈结构

    公开(公告)号：WO2018038785A1

    公开(公告)日：2018-03-01

    申请号：PCT/US2017/035006

    申请日：2017-05-30

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： KAWAMURA, Takeshi ,  FUNAYAMA, Kota

    IPC: H01L27/1158 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support pillar structures are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed over the first tier structure. Memory stack structures and second support pillar structures are formed through the second tier structure. The first and second sacrificial material layers are replaced with first and second electrically conductive layers while the first support pillar structures, the second support pillar structures, and the memory stack structures provide structural support to the first and second insulating layers. By limiting the spatial extent of the first support pillar structures within the first tier structure, electrical short to backside contact via structures can be reduced.

    Abstract translation: 包括第一绝缘层和第一牺牲材料层的第一交替叠层的第一层结构形成在衬底上。 第一支柱结构通过第一层结构形成。 包括第二绝缘层和第二牺牲材料层的第二交替堆叠的第二层结构形成在第一层结构上方。 存储器堆叠结构和第二支撑柱结构通过第二层结构形成。 第一牺牲材料层和第二牺牲材料层被第一导电层和第二导电层替代，而第一支撑柱结构，第二支撑柱结构和存储器堆叠结构为第一绝缘层和第二绝缘层提供结构支撑。 通过限制第一层结构内的第一支撑柱结构的空间范围，可以减少对背面接触通路结构的电短路。

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING COMPOSITE WORD LINES AND MULTI-STRIP SELECT LINES AND METHOD FOR MAKING THE SAME
    5.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING COMPOSITE WORD LINES AND MULTI-STRIP SELECT LINES AND METHOD FOR MAKING THE SAME 审中-公开

    公开(公告)号：WO2020197597A1

    公开(公告)日：2020-10-01

    申请号：PCT/US2019/064411

    申请日：2019-12-04

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： CUI, Zhixin ,  ZHOU, Fei ,  MAKALA, Raghuveer S.

    IPC: H01L29/06 ,  H01L27/06 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/1158

    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

    SELECT TRANSISTORS WITH TIGHT THRESHOLD VOLTAGE IN 3D MEMORY
    6.
    发明申请
    SELECT TRANSISTORS WITH TIGHT THRESHOLD VOLTAGE IN 3D MEMORY 审中-公开
    在三维存储器中选择具有较高阈值电压的晶体管

    公开(公告)号：WO2018071116A1

    公开(公告)日：2018-04-19

    申请号：PCT/US2017/050440

    申请日：2017-09-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： PANG, Liang ,  PACHAMUTHU, Jayavel ,  DONG, Yingda

    IPC: H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/1157

    CPC classification number: H01L27/11519 ,  H01L21/02532 ,  H01L21/0262 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833

    Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

    Abstract translation: 这里公开的是具有选择晶体管的3D存储器及其制造方法。 选择晶体管可以具有导电浮置栅极，导电控制栅极，导电浮置栅极和导电控制栅极之间的第一电介质以及主体和导电浮置栅极之间的第二电介质。 在一个方面中，使用在晶体半导体选择晶体管主体附近的凹槽中的横向外延生长，随后通过外延生长形成栅极电介质来形成均匀的栅极电介质。 技术有助于防止或至少降低选择晶体管控制栅极与选择晶体管下方的选择晶体管主体和/或半导体衬底之间的泄漏电流。 因此，选择具有基本均匀的阈值电压，电流和S因子的晶体管。 另外，选择晶体管具有较高的导通电流和陡峭的亚阈值斜率。

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