A neural-network accelerator die is stacked on and integrated with a high-bandwidth memory so that the stack behaves as a single, three-dimensional (3-D) integrated circuit. The accelerator die includes a high-bandwidth memory (HBM) interface that allows a host processor to store training data and retrieve inference-model and output data from memory. The accelerator die additionally includes accelerator tiles with a direct, inter-die memory interfaces to a stack of underlying memory banks. The 3-D IC thus supports both HBM memory channels optimized for external access and accelerator- specific memory channels optimized for training and inference.