公开(公告)号：WO2009082502A1

公开(公告)日：2009-07-02

申请号：PCT/US2008/055661

申请日：2008-03-03

Applicant: RAMBUS INC. ,  GIOVANNINI, Thomas ,  GUPTA, Alok ,  SHAEFFER, Ian ,  WOO, Steven C.

Inventor： GIOVANNINI, Thomas ,  GUPTA, Alok ,  SHAEFFER, Ian ,  WOO, Steven C.

IPC: G11C7/22 ,  G11C11/40

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. The phase detector on the memory chip receives signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. The phase detector uses the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

Abstract translation: 存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变数据选通确认操作的延迟， 选通相对于时钟信号的时钟周期的倍数。 存储器芯片上的相位检测器从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记时钟信号中的特定时钟周期的脉冲。 相位检测器使用标记信号来画定时钟信号中的特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生反馈信号，该信号被返回到存储器控制器以便于校准 时间关系。

公开(公告)号：WO2010096263A2

公开(公告)日：2010-08-26

申请号：PCT/US2010/022886

申请日：2010-02-02

Applicant: RAMBUS INC. ,  LIN, Qi ,  PENG, Liang ,  HAMPEL, Craig E. ,  SHEFFLER, Thomas J. ,  WOO, Steven C. ,  RYCHLIK, Bohuslav

Inventor： LIN, Qi ,  PENG, Liang ,  HAMPEL, Craig E. ,  SHEFFLER, Thomas J. ,  WOO, Steven C. ,  RYCHLIK, Bohuslav

IPC: G06F15/16 ,  G06F15/173 ,  G06F12/08 ,  G06F15/167

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract translation: 高速缓存一致性协议在共享存储空间的多个处理器（或处理器内核）之间分配原子操作。 当包括修改存储在共享存储空间中的数据的指令的原子操作被引导到不具有对与数据相关联的地址的控制的第一处理器时，第一处理器发送请求，该请求包括指令 修改数据到第二个处理器。 然后，已经控制地址的第二处理器修改数据。 此外，第一个处理器可以立即继续执行另一条指令，而不是等待地址变为可用。

公开(公告)号：WO2023038790A1

公开(公告)日：2023-03-16

申请号：PCT/US2022/041200

申请日：2022-08-23

Applicant: RAMBUS INC.

Inventor： KIM, Joohee ,  LEE, Dongyun ,  WOO, Steven C.

IPC: G06F1/04 ,  G11C7/22 ,  G06F1/08

Abstract: Multiple (e.g., four) memory devices on a module are connected to a common pair of differential data strobe signal conductors. The common pair of differential data strobe conductors are also coupled to a memory controller to time the transmission of data to the multiple memory devices and to time the reception of data from the memory devices. The controller calibrates two or more different data transmission delays relative to its transmission of a write data strobe signal on the common pair of differential data strobe conductors. The controller also calibrates to account for two or more different data reception delays (skew) relative to its reception of a read data strobe signal on the common pair of differential data strobe conductors.

公开(公告)号：WO2009048707A1

公开(公告)日：2009-04-16

申请号：PCT/US2008/075782

申请日：2008-09-10

Applicant: RAMBUS INC. ,  WOO, Steven C. ,  TSANG, Brian Hing-Kit ,  NG, William N. ,  SHAEFFER, Ian

Inventor： WOO, Steven C. ,  TSANG, Brian Hing-Kit ,  NG, William N. ,  SHAEFFER, Ian

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/08 ,  G06F12/1027 ,  G06F2212/2022 ,  G06F2212/205

Abstract: Embodiments of a circuit are described. This circuit includes an instruction fetch unit to fetch instructions to be executed which are associated with one or more virtual addresses, a translation lookaside buffer (TLB), and an execution unit to execute the instructions. Moreover, the TLB converts virtual addresses into physical addresses. Note that the TLB includes entries for physical addresses that are dedicated to dynamic random access memory (DRAM) and entries for physical addresses that are dedicated to a memory having a storage cell with a retention time that decreases as operations are performed on the storage cell.

Abstract translation: 描述电路的实施例。 该电路包括提取单元以提取与一个或多个虚拟地址相关联的要执行的指令，翻译后备缓冲器（TLB）以及执行指令的执行单元。 此外，TLB将虚拟地址转换为物理地址。 注意，TLB包括专用于动态随机存取存储器（DRAM）的物理地址条目和专用于具有存储单元的存储器的物理地址条目，存储单元具有随着对存储单元执行操作而减少的保留时间。

公开(公告)号：WO2021202160A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/023608

申请日：2021-03-23

Applicant: RAMBUS INC.

Inventor： VOGELSANG, Thomas ,  WOO, Steven C. ,  GOPALAKRISHNAN, Liji

IPC: G11C5/06

Abstract: A neural-network accelerator die is stacked on and integrated with a high-bandwidth memory so that the stack behaves as a single, three-dimensional (3-D) integrated circuit. The accelerator die includes a high-bandwidth memory (HBM) interface that allows a host processor to store training data and retrieve inference-model and output data from memory. The accelerator die additionally includes accelerator tiles with a direct, inter-die memory interfaces to a stack of underlying memory banks. The 3-D IC thus supports both HBM memory channels optimized for external access and accelerator- specific memory channels optimized for training and inference.

公开(公告)号：WO2020176291A1

公开(公告)日：2020-09-03

申请号：PCT/US2020/018634

申请日：2020-02-18

Applicant: RAMBUS INC.

Inventor： WOO, Steven C. ,  PARTSCH, Torsten

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16

Abstract: A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.

公开(公告)号：WO2009064619A1

公开(公告)日：2009-05-22

申请号：PCT/US2008/081737

申请日：2008-10-30

Applicant: RAMBUS INC. ,  WOO, Steven C. ,  HAUKNESS, Brent S. ,  CHING, Michael T.

Inventor： WOO, Steven C. ,  HAUKNESS, Brent S. ,  CHING, Michael T.

IPC: G11C7/12 ,  G11C7/18 ,  G11C16/24

CPC classification number: G11C11/4097 ,  G11C7/18 ,  G11C2207/005 ,  G11C2207/2272

Abstract: Embodiments in the present disclosure pertain to an apparatus and method for segmentation of a memory device. A bit line (100) is comprised of at least two bit line segments (102, 103) separated by a segment switch (101). When accessing memory cells (105) coupled to the bit line segment closest to the sense amplifier (104), the switch is non-conducting. Controlling the switch to be non-conducting electrically isolates the other bit line segment, thereby also electrically isolating the capacitance and resistance inherent to that bit line segment from the sense amplifier. By electrically isolating" the capacitance and resistance from the sense amplifier, self-refresh, refresh, and row activation can be performed with less power consumed and lower access latency.

Abstract translation: 本公开的实施例涉及用于分割存储器件的装置和方法。 位线（100）包括由段开关（101）分开的至少两个位线段（102,103）。 当访问耦合到最靠近读出放大器（104）的位线段的存储单元（105）时，开关不导通。 将开关控制为非导通电隔离另一个位线段，从而也将该位线段的固有电容和电阻与读出放大器电隔离。 通过电隔离“感测放大器的电容和电阻，可以以较少的功耗消耗和较低的访问延迟来执行自刷新，刷新和行激活。