公开(公告)号：WO2020112884A1

公开(公告)日：2020-06-04

申请号：PCT/US2019/063419

申请日：2019-11-26

Applicant: RAMBUS INC.

Inventor： VOGELSANG, Thomas

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/408 ,  G11C11/4094 ,  H01L27/108

Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device – thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.

公开(公告)号：WO2015038569A2

公开(公告)日：2015-03-19

申请号：PCT/US2014/054886

申请日：2014-09-10

Applicant: RAMBUS INC.

Inventor： SMITH, Craig, M. ,  GUIDASH, Michael ,  ENDSLEY, Jay ,  VOGELSANG, Thomas ,  HARRIS, James, E.

IPC: H04N5/335

CPC classification number: H04N5/3559 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H04N5/347 ,  H04N5/355 ,  H04N5/3741 ,  H04N5/37455 ,  H04N5/378

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

Abstract translation: 在集成电路图像传感器内的像素阵列中，评估多个像素中的每一个以确定响应于入射光而在像素内积分的电荷是否超过第一阈值。 生成与集成在多个像素的至少一个子集内的电荷相对应的N位数字样本，然后将其应用于查找表以检索各自的M位数字值（M小于N），其中步进范围 由M位数字值的可能状态表示的电荷积分水平从基于第一阈值确定的开始电荷积分水平向上延伸。

公开(公告)号：WO2014144391A1

公开(公告)日：2014-09-18

申请号：PCT/US2014/028780

申请日：2014-03-14

Applicant: RAMBUS INC.

Inventor： VOGELSANG, Thomas ,  GUIDASH, Michael ,  XUE, Song ,  SMIRNOV, Maxim ,  SMITH, Craig, M. ,  ENDSLEY, Jay ,  HARRIS, James, E.

IPC: H04N5/3745 ,  H04N5/347 ,  H01L27/146

CPC classification number: H04N5/3745 ,  H01L27/14634 ,  H01L27/14641 ,  H04N5/347 ,  H04N5/376

Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract translation: 在图像传感器系统中实现具有多位采样的图像传感器架构。 响应于入射到感光元件上的光而产生的像素信号被转换为表示像素信号的多位数字值。 如果像素信号超过采样阈值，则光敏元件被复位。 在图像捕获期间，与超过采样阈值的像素信号相关联的数字值被累积到图像数据中。

公开(公告)号：WO2013062874A1

公开(公告)日：2013-05-02

申请号：PCT/US2012/061212

申请日：2012-10-19

Applicant: RAMBUS INC.

Inventor： TSERN, Ely ,  WARE, Frederick, A. ,  RAJAN, Suresh ,  VOGELSANG, Thomas

IPC: G06F12/00

CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract translation: 公开了一种集成电路（IC）存储器件中的操作方法。 该方法包括以第一刷新率刷新IC存储设备中的第一组存储行。 测试每行的保留时间。 对于给定的被测试行的测试包括以比第一刷新率慢的第二刷新率进行刷新。 基于对给定行测试中存储的数据的访问请求，测试是可中断的。

公开(公告)号：WO2013015893A1

公开(公告)日：2013-01-31

申请号：PCT/US2012/041758

申请日：2012-06-08

Applicant: RAMBUS INC. ,  HARRIS, James, Edward ,  VOGELSANG, Thomas ,  WARE, Frederick, A. ,  SHAEFFER, Ian, P.

Inventor： HARRIS, James, Edward ,  VOGELSANG, Thomas ,  WARE, Frederick, A. ,  SHAEFFER, Ian, P.

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Abstract translation: 存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。 此外，代替激活响应于行命令的子代码，延迟激活操作被延迟，直到接收到指定要执行的列操作的列命令和被激活的子代。

公开(公告)号：WO2022187089A1

公开(公告)日：2022-09-09

申请号：PCT/US2022/017883

申请日：2022-02-25

Applicant: RAMBUS INC.

Inventor： BEST, Scott, C. ,  VOGELSANG, Thomas ,  HAMBURG, Michael, Alexander ,  MARSON, Mark, Evan ,  HANDSCHUH, Helena ,  HAMPEL, Craig, E. ,  WRIGHT, Kenneth, Lee

IPC: G06F21/72 ,  G06F21/78 ,  G06F21/79

Abstract: An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fmgerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.

公开(公告)号：WO2020197925A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/023584

申请日：2020-03-19

Applicant: RAMBUS INC.

Inventor： VOGELSANG, Thomas ,  HAMPEL, Craig, E.

IPC: G06F13/14 ,  G06F13/28 ,  G06F13/16 ,  G06F12/02

Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

公开(公告)号：WO2017192759A1

公开(公告)日：2017-11-09

申请号：PCT/US2017/030902

申请日：2017-05-03

Applicant: RAMBUS INC.

Inventor： WARE, Frederick, A. ,  LINSTADT, John, Eric ,  HAUKNESS, Brent, Steven ,  WRIGHT, Kenneth, L. ,  VOGELSANG, Thomas

IPC: G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4096

CPC classification number: G11C11/403 ,  G06F12/06 ,  G11C5/025 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/18 ,  G11C8/08 ,  G11C11/40618 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

Abstract translation: 存储器组件包括第一存储体。 第一存储体具有多个具有存储元件子行的子阵列。 存储器组件包括耦合到第一存储体的写入驱动器，用于执行子阵列的整个子行的写入操作。 要执行写入操作，写入驱动程序需要将一连串写入数据加载到内存条。 存储体然后可以激活与整个子行的多个存储元件相关联的多个读出放大器，以将写入数据的突发加载到多个读出放大器。

公开(公告)号：WO2016164242A1

公开(公告)日：2016-10-13

申请号：PCT/US2016/025174

申请日：2016-03-31

Applicant: RAMBUS INC.

Inventor： VOGELSANG, Thomas ,  ENDSLEY, Jay ,  GUIDASH, Michael ,  SMITH, Craig, M.

IPC: H04N5/3745 ,  H04N5/353

CPC classification number: H04N5/378 ,  H01L27/14634 ,  H04N5/3532 ,  H04N5/3535 ,  H04N5/35572 ,  H04N5/35581 ,  H04N5/357 ,  H04N5/369

Abstract: Multiple image data subframes corresponding to respective portions of an exposure interval are generated within a sensor device of an image system. Depending on whether the exposure interval exceeds one or more exposure time thresholds, data representative multiple image data subframes are output from the image sensor device in one of at least two formats, including a first format in which each of the subframes of image data is output in its entirety, and a second format in which a logical combination of at least two of the subframes of image data is output instead of the at least two of the subframes of image data such that the total volume of image data output from the image sensor device is reduced relative to the first format.

Abstract translation: 在图像系统的传感器装置内产生与曝光间隔的各个部分对应的多个图像数据子帧。 根据曝光间隔是否超过一个或多个曝光时间阈值，代表多个图像数据子帧的数据以至少两种格式之一从图像传感器装置输出，包括其中输出图像数据的每个子帧的第一格式 以及第二格式，其中输出图像数据的至少两个子帧的逻辑组合，而不是图像数据的至少两个子帧，使得从图像传感器输出的图像数据的总体积 设备相对于第一格式减少。

公开(公告)号：WO2015183693A1

公开(公告)日：2015-12-03

申请号：PCT/US2015/032006

申请日：2015-05-21

Applicant: RAMBUS, INC.

Inventor： VOGELSANG, Thomas ,  SMITH, Craig, M.

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/35581 ,  G06T7/248 ,  H04N5/23232 ,  H04N5/23245 ,  H04N5/2351 ,  H04N5/343 ,  H04N5/347 ,  H04N5/37457 ,  H04N5/378 ,  H04N9/045

Abstract: In an integrated-circuit image sensor having a pixel array, a first subframe readout policy is selected from among a plurality of subframe readout policies, each of the subframe readout policies specifying a first number of subframes of image data to be readout from the pixel array for each output image frame and respective exposure durations for each of the first number of subframes of image data, wherein a shortest one of the exposure durations is uniform for each of the subframe readout policies. Each of the first number of subframes of image data is read out from the pixel array following the respective exposure durations thereof while applying a respective analog readout gain. The analog readout gain applied during readout of at least a first subframe of the first number of subframes is scaled according to a ratio of the shortest one of the exposure durations to the exposure duration of the first subframe.

Abstract translation: 在具有像素阵列的集成电路图像传感器中，从多个子帧读出策略中选择第一子帧读出策略，每个子帧读出策略指定要从像素阵列读出的图像数据的第一数量子帧 对于每个输出图像帧和针对图像数据的第一数量子帧中的每一个的相应曝光持续时间，其中每个子帧读出策略的最短的一个曝光持续时间是均匀的。 在施加相应的模拟读出增益的同时，在其各自的曝光持续时间之后，从像素阵列中读出第一数量的图像数据的子帧。 在第一子帧的至少第一子帧的读出期间应用的模拟读出增益根据第一子帧的曝光持续时间中的最短一个的比率来缩放。