Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device (104) and the host device (102) can include control logic (112, 118) that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.