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公开(公告)号：WO2022047266A1
公开(公告)日：2022-03-03
申请号：PCT/US2021/048112
申请日：2021-08-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： LEE, Hyun Yoo , KIM, Kang-Yong
IPC: G06F11/10 , G11C11/406
Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology (306) to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations (510) to maintain data stored in a memory array (208). A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address (314) can be stored. Responsive to the corresponding address being refreshed, corrected data (312) is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.
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公开(公告)号：WO2020242793A1
公开(公告)日：2020-12-03
申请号：PCT/US2020/033243
申请日：2020-05-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： KIM, Kang-Yong
Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.
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公开(公告)号：WO2023086677A1
公开(公告)日：2023-05-19
申请号：PCT/US2022/049982
申请日：2022-11-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： HATAKEYAMA, Atsushi , LEE, Hyun Yoo , KIM, Kang-Yong , YAMAMOTO, Akiyoshi
IPC: G11C11/406 , G11C11/408 , G06F3/06
Abstract: Disclosed herein is an apparatus that includes a plurality of memory banks and a refresh controller configured to perform a refresh operation on one or more of the plurality of memory banks having a first state without performing the refresh operation on one or more of the plurality of memory banks having a second state responsive to a first refresh command, and perform the refresh operation on a selected one of the plurality of memory banks responsive to a second refresh command. The refresh controller is configured to bring the selected one of the plurality of memory banks into the second state when the refresh operation is performed responsive to the second refresh command.
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公开(公告)号：WO2023064055A1
公开(公告)日：2023-04-20
申请号：PCT/US2022/043083
申请日：2022-09-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： KIM, Kang-Yong , LEE, Hyunyoo
Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.
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公开(公告)号：WO2023009963A1
公开(公告)日：2023-02-02
申请号：PCT/US2022/073994
申请日：2022-07-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： LU, Yang , KIM, Kang-Yong
Abstract: Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.
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Patent Agency Ranking
公开(公告)号：WO2022147000A1
公开(公告)日：2022-07-07
申请号：PCT/US2021/065333
申请日：2021-12-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： KIM, Kang-Yong , LEE, Hyun Yoo , HOLLIS, Timothy M. , LIM, Dong Soon
Abstract: Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit (460) can be coupled between an output and an input of a middle slicer (422). In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye (712) of the PAM4 signal. The other two eyes (710, 714) thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.
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公开(公告)号：WO2022266576A1
公开(公告)日：2022-12-22
申请号：PCT/US2022/072636
申请日：2022-05-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： KIM, Kang-Yong , SONG, Keun Soo , LEE, Hyun Yoo
IPC: G06F1/324 , G06F1/12 , G06F1/3234
Abstract: This document describes apparatuses and techniques for write timing compensation. In various aspects, a write timing compensator (112) of a memory controller (108) can apply a delay to data signals transmitted to a memory circuit (124) based on various operating parameters, which may include voltage or latency information. In some cases, the memory controller (108) or memory circuit (124) powers components of write timing compensation circuitry using a dynamic power rail that scales with an operating voltage of the memory circuit. By so doing, the write timing compensator (112) or compensation circuits (402) may improve signal integrity of data signals communicated between the memory controller and the memory circuit at different frequencies and voltages.
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公开(公告)号：WO2022198193A1
公开(公告)日：2022-09-22
申请号：PCT/US2022/071134
申请日：2022-03-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： SONG, Keun Soo , KIM, Kang-Yong , LEE, Hyun Yoo
Abstract: Described apparatuses and methods provide configurable error correction code, ECC, circuitry (112) and schemes that can utilize a shared ECC engine (408) between two or more memory banks (404) of a memory (110, 208), including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values (412) based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.
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公开(公告)号：WO2022146997A1
公开(公告)日：2022-07-07
申请号：PCT/US2021/065330
申请日：2021-12-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： KIM, Kang-Yong , LEE, Hyun Yoo , HOLLIS, Timothy M. , LIM, Dong Soon
Abstract: Described apparatuses and methods enable communication between a host device (104) and a memory device (108) to establish relative delays between different data lines (304). If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect (106) having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command (122) indicative of a phase offset between two or more data lines (304, 306) of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets (312) between data lines (314, 316). The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.
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公开(公告)号：WO2022047265A1
公开(公告)日：2022-03-03
申请号：PCT/US2021/048111
申请日：2021-08-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： KIM, Kang-Yong , LEE, Hyun Yoo
IPC: G11C11/406 , G11C11/4076 , G06F13/28 , G06F3/06
Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device (104) and the host device (102) can include control logic (112, 118) that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.
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