According to one aspect of the disclosure, a MAC hardware accelerator of a baseband chip is provided. The medium access control (MAC) hardware accelerator may include a MAC-physical (PHY) layer interface configured to receive, from a PHY layer transmitter (Tx), a request for a first number of bytes for a transport block (TB) associated with a component carrier (CC). The MAC hardware accelerator may obtain a MAC protocol data unit (PDU) from a MAC inline buffer associated with the CC. The MAC -PHY layer interface transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the MAC -PHY layer interface may b implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.