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1.发明申请
公开(公告)号：WO2023091125A1
公开(公告)日：2023-05-25
申请号：PCT/US2021/059490
申请日：2021-11-16
Applicant: ZEKU, INC.
Inventor： BAGCHI, Sonali , MA, Tianan Tim , LI, Yunhong , LOW, Su-Lin , LEE, Chun-I , WANG, Yanming , CHEN, Jinghu
Abstract: According to one aspect of the disclosure, a MAC hardware accelerator of a baseband chip is provided. The medium access control (MAC) hardware accelerator may include a MAC-physical (PHY) layer interface configured to receive, from a PHY layer transmitter (Tx), a request for a first number of bytes for a transport block (TB) associated with a component carrier (CC). The MAC hardware accelerator may obtain a MAC protocol data unit (PDU) from a MAC inline buffer associated with the CC. The MAC -PHY layer interface transfer the MAC PDU to the PHY layer Tx during a first period associated with the TB. In response to determining that the MAC inline buffer does not include the first number of bytes, the MAC -PHY layer interface may b implement a recovery mechanism at an end of the first period to maintain synchronization between the MAC hardware accelerator and the PHY layer Tx.
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公开(公告)号：WO2023282888A1
公开(公告)日：2023-01-12
申请号：PCT/US2021/040496
申请日：2021-07-06
Applicant: ZEKU, INC.
Inventor： LOW, Su-lin , LI, Yunhong , HONG, Hausting , LEE, Chun-I , KOVOOR, Sheethal , MA, Tianan , LI, Jianzhou , BAGCHI, Sonali , PAO, Sammy, Tzu-Kiang , CHEN, Na , KI, Sangwon , WANG, Zengyu , SURESHCHANDRAN, Swaminathan , WEE, Sun, Hee
Abstract: According to one aspect of the present disclosure, a baseband chip including a downlink (DL) Layer 2 block is disclosed. The DL Layer 2 block may include a buffer configured to receive a DL Layer 2 protocol data unit (PDU) from a Medium Access Control (MAC) circuit. The DL Layer 2 block may also include a microcontroller. The microcontroller may be configured to determine whether a DL Layer 2 processing circuit is active. The microcontroller may be further configured to delay an activation of the DL Layer 2 processing circuit until a trigger event occurs when it is determined that the DL Layer 2 processing circuit is inactive. The DL Layer 2 block may further include a DL Layer 2 processing circuit. The DL Layer 2 processing circuit may be configured to fetch the PDU from the buffer when activated. The DL Layer 2 processing circuit may be further configured to perform Layer 2 processing of the PDU.
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Patent Agency Ranking3.发明申请
公开(公告)号：WO2023003543A1
公开(公告)日：2023-01-26
申请号：PCT/US2021/042443
申请日：2021-07-20
Applicant: ZEKU, INC.
Inventor： LOW, Su-Lin , LEE, Chun-I , LI, Yunhong , HONG, Hausting , MA, Tianan, Tim , BAGCHI, Sonali , PAO, Sammy, Tzu-Kiang , KOVOOR, Sheethal , CHEN, Na , KI, Sangwon , HONG, Youn, Ki
Abstract: According to one aspect of the present disclosure, a baseband chip including a downlink (DL) Layer 2 block is disclosed. The DL Layer 2 block may include a set of DL Layer 2 microcontrollers that may activate when an enhanced mobile broadband (eMBB)/normal packet is received. The set of DL Layer 2 microcontrollers may be further configured to perform pipelined processing of the eMBB/normal packet. The set of DL Layer 2 microcontrollers may deactivate when a subsequent eMBB/normal packet is not received after a first period. The DL Layer 2 block may include a set of DL Layer 2 cores that may activate when a ultra-reliable low latency communication (URLLC) packet is received. The set of DL Layer 2 cores may perform parallel processing of the URLLC packet. The set of DL Layer 2 cores may deactivate when a subsequent URLLC packet is not received after a second period.
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4.发明申请
公开(公告)号：WO2023009117A1
公开(公告)日：2023-02-02
申请号：PCT/US2021/043576
申请日：2021-07-28
Applicant: ZEKU, INC.
Inventor： CHEN, Na , LOW, Su-Lin , LEE, Chun-I , LI, Yunhong , MA, Tianan, Tim , BAGCHI, Sonali
Abstract: According to one aspect of the disclosure, a baseband chip is provided. The baseband chip may include a set of transmission command queues each associated with a different component carrier (CC) and each configured to maintain packet descriptors associated with one of the different component carriers (CCs). The baseband chip may also include a Layer 2 microcontroller. The Layer 2 microcontroller may be configured to generate the packet descriptors for each of the different CCs based on associated uplink (UL) grant indicators. The Layer 2 microcontroller may be configured to send each of the packet descriptors to the set of transmission command queues based on CC. The Layer 2 microcontroller may be configured to select a credit-based scheduling mechanism from a set of credit-based scheduling mechanisms. The Layer 2 microcontroller may be configured to configure a transmission scheduler with the credit-based scheduling mechanism.
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5.发明申请
公开(公告)号：WO2023287422A8
公开(公告)日：2023-01-19
申请号：PCT/US2021/041892
申请日：2021-07-15
Applicant: ZEKU, INC.
Inventor： LOW, Su-Lin , CHEN, Na , LI, Yunhong , MA, Tianan Tim , PAO, Sammy Tzu-Kiang
Abstract: According to one aspect of the disclosure, a baseband chip is provided. The baseband chip may include a Layer 2 hardware circuit configured to perform Layer 2 packet processing. The baseband chip may also include a resource prediction circuit. The resource prediction circuit may include a resource mapping circuit. The resource mapping circuit may be configured to receive a grant indication associated with one or more grant conditions. The resource mapping circuit may be configured to identify a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware circuit. The resource mapping circuit may be configured to trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware circuit.
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6.发明申请
公开(公告)号：WO2023287422A1
公开(公告)日：2023-01-19
申请号：PCT/US2021/041892
申请日：2021-07-15
Applicant: ZEKU, INC.
Inventor： LOW, Su-Lin , CHEN, Na , LI, Yunhong , MA, Tianan, Tim , PAO, Sammy, Tzu-Kiang
IPC: H04W36/00
Abstract: According to one aspect of the disclosure, a baseband chip is provided. The baseband chip may include a Layer 2 hardware circuit configured to perform Layer 2 packet processing. The baseband chip may also include a resource prediction circuit. The resource prediction circuit may include a resource mapping circuit. The resource mapping circuit may be configured to receive a grant indication associated with one or more grant conditions. The resource mapping circuit may be configured to identify a resource mapping table associated with the one or more grant conditions. In some embodiments, the resource mapping table may indicate a resource level ratio for a set of Layer 2 resources associated with the Layer 2 hardware circuit. The resource mapping circuit may be configured to trigger a first resource level change of the set of Layer 2 resources associated with the Layer 2 hardware circuit.
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公开(公告)号：WO2022225500A1
公开(公告)日：2022-10-27
申请号：PCT/US2021/027857
申请日：2021-04-18
Applicant: ZEKU, INC.
Inventor： LOW, Su-Lin , LEE, Chun-I , LI, Yunhong , MA, Tianan , BAGCHI, Sonali , CHEN, Na , KI, Sangwon
IPC: H04L12/00 , H04L12/70 , H04L12/861 , H04L12/865 , H04L12/911
Abstract: An apparatus for wireless communication is disclosed. The apparatus may include, among other things, a first logical channel packet (LCP) module and a second LCP module. The first LCP module may dequeue a first slice of a first LCP from a first logical channel (LC) queue until a first threshold condition is met. The first LCP module may send a first LCP indicator to an LCP priority queue when the first slice of the first LCP does not include an entirety of the first LCP. The first LCP indicator may indicate a first remaining slice of the first LCP. The second LCP module dequeue a first slice of a second LCP from a second LC queue until a second threshold condition is met. The first LCP module may dequeue a second slice of the first LCP from the second LC queue until a third threshold condition is met.
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