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1047 条记录 (耗时 0.017 秒)

    HIGH SPEED PRECISION DRILLING SYSTEM
    4.
    发明授权
    HIGH SPEED PRECISION DRILLING SYSTEM 失效
    高速精密钻井系统

    公开(公告)号：EP0266397B1

    公开(公告)日：1992-04-01

    申请号：EP87903101.1

    申请日：1987-04-09

    申请人： DYNAMOTION CORPORATION

    发明人： KOSMOWSKI, Wojciech

    IPC分类号： B23B31/14 ,  B23B47/06 ,  B23Q1/18 ,  B23Q3/157 ,  B25B11/00 ,  B65D85/28 ,  H02K41/02

    CPC分类号： F16C32/06 ,  B23B31/14 ,  B23B39/161 ,  B23Q1/03 ,  B23Q1/032 ,  B23Q1/38 ,  B23Q1/4828 ,  B23Q1/70 ,  B23Q3/15526 ,  B23Q3/15706 ,  B25B11/005 ,  F16C29/025 ,  F16C32/0603 ,  F16C2322/39 ,  H02K7/12 ,  H05K3/0047 ,  Y10T279/17231 ,  Y10T279/247 ,  Y10T408/08 ,  Y10T408/554 ,  Y10T408/675 ,  Y10T408/907 ,  Y10T483/10 ,  Y10T483/179 ,  Y10T483/1864

    摘要： A high speed system (50) for drilling of very small holes in workpieces (137) such as printed circuit boards. The X-Y positioning system includes air bearings (120) to provide lift between the stationary guide beams (60, 62), the cross beam (65), and the top table (70), and further includes a vacuum preloading apparatus (128). The top table (70) is a light honeycomb structure (71, 72, 73), whose effective rigidity is virtually that of the guide beams (60, 62) due to the vacuum preloading. The system (50) includes a conventional spindle (85) and a high speed spindle (81). The high speed spindle (81) includes a stationary body (156) carrying the stator (195, 196) of the drive motor. Only the spindle rotor (160) is translated along the Z axis to perform drilling movements. The rotor (160) is supported within the body (156) by rotary and linear air bearings (179, 187), and is axially driven by a linear motor (210, 220). A tool changer (95) loaded by clips (350) carrying the drilling bits (400) is mounted on the top work table (70). A vacuum hold-down apparatus (140) secures the workpieces (137) to a drilling station.

    摘要翻译： 一种高速系统（50），用于在诸如印刷电路板的工件（137）上钻出非常小的孔。 X-Y定位系统包括空气轴承（120），以在固定导向梁（60,62），横梁（65）和顶部工作台（70）之间提供升降，并且还包括真空预加载装置（128）。 顶台（70）是轻质蜂窝结构（71,72,73），由于真空预加载，其有效刚性实际上是导向梁（60,62）的有效刚度。 系统（50）包括传统的主轴（85）和高速主轴（81）。 高速主轴（81）包括承载驱动马达的定子（195,196）的静止主体（156）。 只有主轴转子（160）沿Z轴平移进行钻孔运动。 转子160由旋转线性空气轴承179和线性空气轴承187支撑在主体156内，并且由线性马达210,220轴向地驱动。 由承载钻头（400）的夹子（350）加载的工具更换器（95）安装在顶部工作台（70）上。 真空压紧装置（140）将工件（137）固定在钻孔台上。

    WAFER-SCALE INTEGRATED CIRCUIT MEMORY
    7.
    发明授权
    WAFER-SCALE INTEGRATED CIRCUIT MEMORY 失效
    超大规模集成电路存储器

    公开(公告)号：EP0229144B1

    公开(公告)日：1992-01-15

    申请号：EP86904285.3

    申请日：1986-07-11

    申请人： ANAMARTIC LIMITED

    发明人： BRENT, Michael ,  MACDONALD, Neal

    IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C11/406 ,  G06F11/20

    CPC分类号： G11C8/00 ,  G11C7/00 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C29/006

    摘要： A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighbouring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated. Each module includes a memory unit (23) including a free running address counter. When the WRITE command appears a data stream on the transmit path is read into the memory. When READ appears, the contents of the memory are read out onto the return path. Memory refresh occurs conventionally under control of the free-running address counter. In order to avoid heavy current in any of the power distribution conductors on the wafer, the count cycles of the free-running address counters are staggered.

    RANDOM ADDRESS SYSTEM FOR CIRCUIT MODULES
    10.
    发明授权
    RANDOM ADDRESS SYSTEM FOR CIRCUIT MODULES 失效
    电路模块随机寻址系统

    公开(公告)号：EP0261164B1

    公开(公告)日：1991-07-24

    申请号：EP87901599.8

    申请日：1987-03-18

    申请人： ANAMARTIC LIMITED

    发明人： SINCLAIR, Alan, Welsh

    IPC分类号： G06F11/20

    CPC分类号： G11C29/006

    摘要： The wafer scale integrated circuit comprises an array of undiced chips or modules (10), each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels (11) for data and control signals exist between each module and its (N, S, E and W) neighbours and a target module in the array may be addressed by setting up a path (12) through the array from an entry module to the target module. The addressing is effected by sending a stream of link commands, each of which tells a module to link on to its (N, S, E or W) neighbour. Each module responds to the first command of the stream and then sends on the stream stripped of this first command. In an alternative embodiment the link commands are transmitted from module to module in parallel, each module responds to the command at the least significant end and strips it off by a shift of the commands in the least significant direction before the commands pass to the next module. A control circuit for addressing modules in the array at random forms a unique set of link commands for each module to be addressed, these command sets being such that the paths to the various modules form a densely branching tree commencing from the entry module.