公开(公告)号：EP4425495A1

公开(公告)日：2024-09-04

申请号：EP24153781.0

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： KIM, Ki-Heung ,  OH, Taeyoung ,  KIM, Taekwoon ,  YUN, Jinseong ,  JEONG, Yoonjae ,  HWANG, Hyongryol

IPC: G11C5/04 ,  G11C7/24 ,  G11C8/12 ,  G11C17/18 ,  G11C7/10 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C2029/440220130101 ,  G11C5/04 ,  G11C8/12 ,  G11C17/18 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/781

Abstract: A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from a memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

公开(公告)号：EP4411570A1

公开(公告)日：2024-08-07

申请号：EP22888834.3

申请日：2022-06-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： CHENG, Long ,  YANG, Ling ,  LI, Yi ,  TAN, Haibo ,  PU, Guiyou

IPC: G06F18/00 ,  G06F7/04

CPC classification number: Y02D10/00 ,  G11C7/06 ,  G06F7/02 ,  G06F18/22 ,  G11C8/12

Abstract: Embodiments of this application disclose a similarity calculation apparatus and method, and a storage device, and relate to the computer field. A specific solution is as follows: The similarity calculation apparatus includes an input signal processing module, a data calculation module, and at least one output processing circuit that are sequentially coupled, where the data calculation module includes a storage array configured to store to-be-calculated data; the input signal processing module is configured to: generate an operating voltage based on similarity calculation instructions, and convert an address of the to-be-calculated data in the similarity calculation instructions into a target address; the data calculation module is configured to: select, based on the target address, the to-be-calculated data stored in the storage array, and apply the operating voltage to the to-be-calculated data to perform similarity calculation; and the at least one output processing circuit is configured to: process a signal output by the data calculation module, and output a calculation result.

公开(公告)号：EP3382711A1

公开(公告)日：2018-10-03

申请号：EP18155639.0

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： SWAMINATHAN, Muthukumar P. ,  KHOCHARE, Kunal A.

IPC: G11C8/12 ,  G11C16/08

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0688 ,  G06F13/1668 ,  G11C8/12 ,  G11C16/08 ,  G11C16/20

Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.

公开(公告)号：EP3333852A1

公开(公告)日：2018-06-13

申请号：EP16202348.5

申请日：2016-12-06

Applicant: Axis AB

Inventor： Hovmöller, Henrik

IPC: G11C5/04 ,  G11C8/12 ,  H05K1/02

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C8/06 ,  G11C8/12 ,  H01L27/0207 ,  H05K1/0243 ,  H05K2201/09327 ,  H05K2201/10159 ,  H05K2201/10545

Abstract: A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed Circuit Board, PCB. A first memory chip (M1) is arranged on a first surface of the PCB, a second memory chip (M2) is arranged on a second surface of the PCB. The second memory chip (M2) is placed back to back to the first memory chip (M1) and oriented such that respective pins having the same function on the first memory chip (M1) and the second memory chip (M2) are placed opposite to each other and connected by vias to respective signal traces arranged between the first and second surfaces of the PCB.

公开(公告)号：EP3210209A4

公开(公告)日：2018-05-16

申请号：EP15852706

申请日：2015-10-07

Applicant: MICRON TECHNOLOGY INC

Inventor： PAN FENG ,  PARK JAEKWAN ,  GHODSI RAMIN

IPC: G11C8/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C8/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.

公开(公告)号：EP3314446A1

公开(公告)日：2018-05-02

申请号：EP16814998.7

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： TOMISHIMA, Shigeki ,  LU, Shih-Lien ,  BAINS, Kuljit S.

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G11C7/08 ,  G11C7/1018 ,  G11C7/1021 ,  G11C7/1045 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/409

Abstract: A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.

公开(公告)号：EP3295310A1

公开(公告)日：2018-03-21

申请号：EP16793186

申请日：2016-05-02

Applicant: ADESTO TECH CORPORATION

Inventor： INTRATER GIDEON ,  PEDERSEN BARD ,  HOLLMER SHANE ,  LEWIS DERRIC ,  TRINH STEPHEN

IPC: G06F11/10 ,  G06C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C8/16 ,  G11C11/41

CPC classification number: G11C7/22 ,  G11C5/141 ,  G11C8/12 ,  G11C11/419 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2209 ,  G11C2211/5623 ,  G11C2216/22

Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.

公开(公告)号：EP3140743A4

公开(公告)日：2018-01-10

申请号：EP15789174

申请日：2015-05-07

Applicant: MICRON TECHNOLOGY INC

Inventor： LEIDEL JOHN ,  MURPHY RICHARD C

IPC: G06F12/06

CPC classification number: G06F12/0817 ,  G06F12/0828 ,  G06F13/16 ,  G06F13/1663 ,  G06F13/40 ,  G06F13/4022 ,  G06F2212/622 ,  G11C5/025 ,  G11C8/12 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

公开(公告)号：EP3084767A4

公开(公告)日：2017-07-19

申请号：EP14872245

申请日：2014-11-06

Applicant: INTEL CORP

Inventor： SCHAEFER ANDRE ,  YEH JEN-CHIEH ,  LUO PEI-WEN

IPC: G11C11/4063 ,  G11C5/06 ,  G11C7/10 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097

CPC classification number: G11C7/1072 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/107 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.

Abstract translation: 公开了访问动态随机存取存储器（DRAM）阵列的示例。 在一些示例中，DRAM组的子阵列可以能够响应于相同的列地址选通而打开多个页面。 在其他示例中，DRAM排的子阵列可以被布置为使得输入/输出（IO）比特可以通过IO线以串行方式被路由。 对于这些其他示例，IO线可以穿过包括DRAM组的DRAM裸片和/或可以耦合到DRAM裸片外部的存储器通道或总线。 描述并要求保护其他示例。

公开(公告)号：EP3039685A1

公开(公告)日：2016-07-06

申请号：EP14839348.1

申请日：2014-08-13

Applicant: Micron Technology, Inc.

Inventor： MANNING, Troy A.

IPC: G11C15/00

CPC classification number: G11C8/10 ,  G06F9/30 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0888 ,  G06F13/40 ,  G06F2212/7202 ,  G11C7/06 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/419 ,  G11C15/04 ,  G11C2207/2245 ,  Y02D10/13

Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

Abstract translation: 本公开的示例提供了用于访问存储器阵列地址空间的设备和方法。 一种示例性存储器阵列，其包括第一地址空间，该第一地址空间包括耦合到第一数量的选择线和多条感测线的存储器单元，以及包括耦合到第二数量的选择线的存储器单元和感测线的数量的第二地址空间 。 第一地址空间相对于第二地址空间可独立地寻址。