利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.012 秒)

    SYSTEM ON A CHIP WITH ALWAYS-ON PROCESSOR
    2.
    发明公开
    SYSTEM ON A CHIP WITH ALWAYS-ON PROCESSOR 审中-公开
    系统AUF EINEM CHIP MIT STETS EINGESCHALTETEM PROZESSOR

    公开(公告)号：EP3146408A1

    公开(公告)日：2017-03-29

    申请号：EP15716364.3

    申请日：2015-04-01

    申请人： Apple Inc.

    发明人： TRIPATHI, Brijesh ,  KEIL, Shane J. ,  GULATI, Manu ,  CHO, Jung Wook ,  MACHNICKI, Erik P. ,  HERBECK, Gilbert H. ,  MILLET, Timothy J. ,  DE CESARE, Joshua P. ,  DALAL, Anand

    IPC分类号： G06F1/32

    CPC分类号： G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

    摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

    摘要翻译： 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以过滤所捕获的传感器数据。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

    ALWAYS-ON AUDIO CONTROL FOR MOBILE DEVICE
    3.
    发明公开
    ALWAYS-ON AUDIO CONTROL FOR MOBILE DEVICE 审中-公开
    永远在线音频控制移动设备

    公开(公告)号：EP3069226A1

    公开(公告)日：2016-09-21

    申请号：EP14786399.7

    申请日：2014-09-29

    申请人： Apple Inc.

    发明人： MILLET, Timothy J. ,  GULATI, Manu

    IPC分类号： G06F3/16 ,  G06F1/32 ,  G10L15/22

    摘要： In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

    MEMORY POWER SAVINGS IN IDLE DISPLAY CASE
    4.
    发明公开
    MEMORY POWER SAVINGS IN IDLE DISPLAY CASE 审中-公开
    内存省电在IDLE显示案例

    公开(公告)号：EP3309674A1

    公开(公告)日：2018-04-18

    申请号：EP17205934.7

    申请日：2014-04-03

    申请人： Apple Inc.

    发明人： BISWAS, Sukalpa ,  SHIU, Shinye ,  DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  DESAI, Pulkit ,  HU, Rong Zhang

    IPC分类号： G06F3/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/00

    CPC分类号： G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

    摘要： In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

    摘要翻译： 在一个实施例中，一种系统包括：存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示器控制器。 系统可以被配置为检测正被显示的图像基本上是静态的，并且可以被配置为使得显示控制器向存储器高速缓存中请求分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时候，帧缓冲器数据可能不会被缓存在存储器缓存中，并且电源管理配置可以允许关闭/减小存储器缓存中的尺寸。

    CLOCK SWITCHING IN ALWAYS-ON COMPONENT
    6.
    发明公开
    CLOCK SWITCHING IN ALWAYS-ON COMPONENT 审中-公开
    时钟切换始终开启组件

    公开(公告)号：EP3257045A1

    公开(公告)日：2017-12-20

    申请号：EP15882269.2

    申请日：2015-12-17

    申请人： Apple Inc.

    发明人： GULATI, Manu ,  HERBECK, Gilbert H. ,  KOSUT, Alexei E. ,  JONES, Girault W. ,  MILLET, Timothy J.

    IPC分类号： G10L25/78 ,  G06F3/16 ,  G10L15/28

    CPC分类号： G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

    摘要： In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

    MEMORY POWER SAVINGS IN IDLE DISPLAY CASE
    9.
    发明公开
    MEMORY POWER SAVINGS IN IDLE DISPLAY CASE 有权
    在LEERLAUFANZEIGEGEHÄUSE的SPEICHERLEISTUNGSEINSPARUNGEN

    公开(公告)号：EP2994825A1

    公开(公告)日：2016-03-16

    申请号：EP14726041.8

    申请日：2014-04-03

    申请人： Apple Inc.

    发明人： BISWAS, Sukalpa ,  SHIU, Shinye ,  DE LA CROPTE DE CHANTERAC, Cyril ,  GULATI, Manu ,  DESAI, Pulkit ,  HU, Rong Zhang

    IPC分类号： G06F3/14 ,  G09G5/393 ,  G09G5/395 ,  G09G5/00

    CPC分类号： G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

    摘要： In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

    摘要翻译： 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/减小大小。