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1.发明公开Semiconductor integrated circuit device for supplying a bias current to DA converters 失效用于向DA转换器提供偏置电流的半导体集成电路设备
公开(公告)号：EP0458659A3
公开(公告)日：1993-08-11
申请号：EP91400494.0
申请日：1991-02-22
发明人： Gotoh, Kunihiko , Sekido, Yuuji
CPC分类号： H03M1/0604 , G05F3/262 , H03M1/662 , H03M1/742
摘要： A semiconductor integrated circuit device comprising a bias generating circuit having an operational amplifier connected to receive an input voltage at its inverting input terminal to produce a gate voltage, a field effect transistor having its gate connected to receive the gate voltage from said operational amplifier and its drain connected to a resistor and to a noniverting input terminal of said operational amplifier, and further field effect transistor having its gate connected to receive the gate voltage from said operational amplifier to produce a current corresponding to the input voltage, one group of current sources responsive to an output voltage of said bias generating circuit to produce a plurality of currents of an equal magnitude and one switching circuit responsive to an input digital value to selectively output the currents from said group of current sources to its common output.
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2.发明授权Semiconductor integrated circuit device for supplying a bias current to DA converters 失效用于数字到模拟转换器提供偏置电流的半导体集成电路装置
公开(公告)号：EP0458659B1
公开(公告)日：1997-10-29
申请号：EP91400494.0
申请日：1991-02-22
发明人： Gotoh, Kunihiko , Sekido, Yuuji
CPC分类号： H03M1/0604 , G05F3/262 , H03M1/662 , H03M1/742
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3.发明公开Semiconductor integrated circuit device for supplying a bias current to DA converters 失效HalbleiterintegriertesSchaltungsgerätzur Versorgung eines Bias-StromsfürDigital-Analogwandler。
公开(公告)号：EP0458659A2
公开(公告)日：1991-11-27
申请号：EP91400494.0
申请日：1991-02-22
发明人： Gotoh, Kunihiko , Sekido, Yuuji
CPC分类号： H03M1/0604 , G05F3/262 , H03M1/662 , H03M1/742
摘要： A semiconductor integrated circuit device comprising a bias generating circuit having an operational amplifier connected to receive an input voltage at its inverting input terminal to produce a gate voltage, a field effect transistor having its gate connected to receive the gate voltage from said operational amplifier and its drain connected to a resistor and to a noniverting input terminal of said operational amplifier, and further field effect transistor having its gate connected to receive the gate voltage from said operational amplifier to produce a current corresponding to the input voltage, one group of current sources responsive to an output voltage of said bias generating circuit to produce a plurality of currents of an equal magnitude and one switching circuit responsive to an input digital value to selectively output the currents from said group of current sources to its common output.
摘要翻译： 一种半导体集成电路器件，包括偏置产生电路，该偏置产生电路具有连接以在其反相输入端接收输入电压以产生栅极电压的运算放大器;场效应晶体管，其栅极连接以接收来自所述运算放大器的栅极电压， 漏极连接到所述运算放大器的电阻器和非输入输入端子，以及另外的场效应晶体管，其栅极连接以接收来自所述运算放大器的栅极电压，以产生对应于输入电压的电流，一组电流源响应 到所述偏置产生电路的输出电压，以响应于输入数字值产生相等幅度的多个电流和一个开关电路，以选择性地将来自所述一组电流源的电流输出到其公共输出。
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公开(公告)号：EP0161947B1
公开(公告)日：1991-07-31
申请号：EP85400383.7
申请日：1985-02-28
申请人： FUJITSU LIMITED
CPC分类号： G11C17/16
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公开(公告)号：EP0213954A3
公开(公告)日：1989-10-18
申请号：EP86306774.0
申请日：1986-09-02
申请人： FUJITSU LIMITED
发明人： Kobayashi, Osamu , Gotoh, Kunihiko
摘要： In an electronic conversion circuit for converting an analog value to digital codes or digital codes to an analog value, the circuit comprises at least two analog processing units (11A, 11B) providing conversion hold blocks. Each of the analog processing units (11A, 11B) has two functions, that is, one function is to perform sampling of an analog value and to circularly convert the analog value to an output analog value in order to obtain a digital value based on the output analog value by a cyclic A/D conversion method, and the other function is to sequentially input digital codes and to convert digital codes in order to obtain an analog value.
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公开(公告)号：EP0194134A2
公开(公告)日：1986-09-10
申请号：EP86301537.6
申请日：1986-03-05
申请人： FUJITSU LIMITED
IPC分类号： H03K19/094
CPC分类号： H03K19/0948 , H03K19/018521
摘要： @ A semiconductor integrated circuit including: an inverter circuit (1) including first and second transistors (T 7 , T 8 ) of different conductivities, and a level shift circuit (2), the first transistor (T 7 ) being supplied with an input signal (IN) via the level shift circuit (2), the second transistor (T 8 ) being supplied with the input signal (IN) directly, and the level shift circuit (2) having an amount of level shift such that, when an input signal (IN) corresponding to an «H» logic level is received, the level of the input signal supplied via the level shift circuit (V A ) is shifted near to the threshold level of the first transistor (T 7 ), to ensure correct switching of the first transistor (T 7 ). The level shift circuit (2) may be formed by a level divider circuit (T 1 , T 2 , T 3 ) and a source follower circuit (T 4 , T 5 ).
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7.发明公开Reader device, its transmission method, and tag 有权EinLesegerät，seine entsprechendeÜbertragungsmethodeund ein Kooperierendes HF Etikett
公开(公告)号：EP1607764A1
公开(公告)日：2005-12-21
申请号：EP05004799.2
申请日：2005-03-04
申请人： FUJITSU LIMITED
CPC分类号： G06K7/0008 , G01S13/758 , G06K7/10297 , G06K19/0723 , Y02D70/10
摘要： A reader device (100) and RF tag (400) improves the efficiency of frequency usage without increasing bandwidth using wireless communication from the reader to the tag and provides a transmission method that improves the power supply efficiency from the reader to the tag to extend the communication distance from the tag to the reader. A reader device for wirelessly communicating with an RF tag, comprises circuitry operable to transmit a wireless signal including information indicating encoding method of data to the RF tag and circuitry operable to receive and demodulate a wireless signal from the RF tag.
摘要翻译： 读取器设备（100）和RF标签（400）提高频率使用的效率，而不用增加使用从读取器到标签的无线通信的带宽，并提供一种传输方法，其提高从读取器到标签的电源效率， 从标签到阅读器的通信距离。 一种用于与RF标签无线通信的读取器装置，包括可操作以将包括指示数字的编码方式的信息的无线信号发射到RF标签的电路和可操作以从RF标签接收和解调无线信号的电路。
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公开(公告)号：EP0372956B1
公开(公告)日：1995-08-23
申请号：EP89312758.9
申请日：1989-12-07
申请人： FUJITSU LIMITED
IPC分类号： G05F3/20
CPC分类号： G05F3/20
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公开(公告)号：EP0318396A3
公开(公告)日：1990-03-21
申请号：EP88402978.6
申请日：1988-11-25
申请人： FUJITSU LIMITED
发明人： Kobayashi, Osamu , Gotoh, Kunihiko
IPC分类号： H03F1/30
CPC分类号： H03F1/308
摘要： An operational amplifier circuit comprises a differential amplifier circuit (1) for generating an output voltage (V₂) in response to the difference in potential between two input signals (+IN, -IN), a level shift circuit (2) for shifting the output voltage of the differential amplifier circuit, a push-pull output circuit (3) which operates in response to the output voltages of the differential amplifier circuit and the level shift circuit, and a bias circuit (4) for generating a bias voltage (V B ) in response to a power supply voltage (V DD ) to control the level shift circuit. The output voltage of the level shift circuit is not affected by fluctuations of the power supply voltage.
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公开(公告)号：EP0192456A3
公开(公告)日：1989-04-05
申请号：EP86301107.8
申请日：1986-02-18
申请人： FUJITSU LIMITED
发明人： Saito, Tadahiro , Gotoh, Kunihiko
摘要： In a semiconductor integrated circuit (10) comprising an internal circuit (9), an oscillating circuit (1) generating a basic clock signal for operating the internal circuit (9) when the internal circuit is operated in a usual mode, a pair of terminals (Toscin, Toscout) connected to the input side and output side of the oscillating circuit (1), respectively, an oscillator (8) being connected between the above pair of terminals (Toscin, Toscout) when the internal circuit (9) is , operated in a usual mode, a reset terminal (Treset) through which a reset signal for resetting the internal circuit is supplied from outside the integrated circuit (10) to the internal circuit, and a test circuit (3, 4, 5) for operating the internal circuit (9) in a test mode; the test circuit supplies a clock signal for testing from outside the integrated circuit to the internal circuit (9) through one of the above pair of terminals (Toscout) when signals of a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals (Toscin) and the reset terminal (Treset).
摘要翻译： 在包括内部电路（9）的半导体集成电路（10）中，当内部电路以通常模式工作时产生用于操作内部电路（9）的基本时钟信号的振荡电路（1），一对端子 （Toscin，Toscout），分别连接到振荡电路（1）的输入侧和输出侧;振荡器（8），当内部电路（9）接通时，连接在上述一对端子（Toscin，Toscout） 以正常模式操作;复位端子（Treset），通过该复位端子将用于复位内部电路的复位信号从集成电路（10）外部提供给内部电路;以及测试电路（3,4,5），用于操作 内部电路（9）处于测试模式; 当预定电平的信号从芯片的外部提供给测试电路时，测试电路通过上述一对端子（Toscout）中的一个将从集成电路外部测试的时钟信号提供给内部电路（9） 上述一对端子中的另一个（Toscin）和复位端子（Treset）中的每一个。
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