利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

74 条记录 (耗时 0.015 秒)

    INTEGRATOR AND ANALOG-TO-DIGITAL CONVERTER
    1.
    发明公开
    INTEGRATOR AND ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：EP3940959A1

    公开(公告)日：2022-01-19

    申请号：EP21185102.7

    申请日：2021-07-12

    申请人： Silergy Semiconductor Technology (Hangzhou) Ltd

    发明人： HUANG, Ying ,  GAO, Di ,  LI, Kun ,  QIN, Jinyu

    IPC分类号： H03M1/40 ,  H03M1/14 ,  H03M1/66 ,  H03M3/00 ,  H03F3/45 ,  H03M1/12 ,  H03M1/06

    摘要： An integrator and an analog-to-digital converter are provided. The analog-to-digital converter includes the integrator, a comparison circuit and a control logic circuit. The integrator includes an operational amplifier, offset capacitors, input capacitors, integral capacitors and controllable switches. The input capacitors and the integral capacitors are connected to the operational amplifier via controllable switches, so that the integrator operates in various operation modes. Operation states of the offset capacitors in a first phase and a second phase of an operation cycle are controlled by switching on or off the controllable switches. Therefore, an offset voltage of the integrator is eliminated, and conversion efficiency and conversion accuracy of the analog-to-digital converter is improved.

    PROCESSING CIRCUITRY
    4.
    发明公开
    PROCESSING CIRCUITRY 审中-公开

    公开(公告)号：EP3514963A1

    公开(公告)日：2019-07-24

    申请号：EP18152587.4

    申请日：2018-01-19

    申请人： Socionext Inc.

    发明人： LINKEWITSCH, Niklas ,  DRÖGE, Guido ,  DEDIC, Charles Joseph

    IPC分类号： H03M1/06 ,  H03M1/08 ,  H03M1/46 ,  H03M1/40 ,  H03M1/80

    摘要： Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

    VOLTAGE DOUBLING CIRCUIT FOR AN ANALOG TO DIGITAL CONVERTER (ADC)
    5.
    发明公开
    VOLTAGE DOUBLING CIRCUIT FOR AN ANALOG TO DIGITAL CONVERTER (ADC) 审中-公开
    EANEN模拟数字万用表（ADC）SPANUNGSVERDOPPLUNGSSCHALTUNGFÜR

    公开(公告)号：EP3111558A1

    公开(公告)日：2017-01-04

    申请号：EP15706980.8

    申请日：2015-02-09

    申请人： Qualcomm Incorporated

    发明人： ALLADI, Dinesh Jagannath ,  BAKER, Sean ,  SIVAKUMAR, Balasubramanian ,  HUANG, Wei ,  YUAN, Dan

    IPC分类号： H03M1/06 ,  H03M1/46 ,  H03M1/40

    CPC分类号： H03M1/1245 ,  H03M1/0682 ,  H03M1/38 ,  H03M1/403 ,  H03M1/468 ,  H03M1/66

    摘要： In one embodiment, a circuit includes a first input of a comparator for an analog to digital converter (ADC). The first input is coupled to a first capacitive network. The circuit further includes a second input of the comparator for the ADC. The second input is coupled to a second capacitive network. The first capacitive network includes a first set of capacitors where a first plate of the first set of capacitors is selectively coupled to an input signal. The second capacitive network includes a second set of capacitors where a second plate of the first set of capacitors is selectively coupled to the input signal. The first plate and the second plate are opposite plates of the first set of capacitors and the second set of capacitors.

    摘要翻译： 在一个实施例中，电路包括用于模数转换器（ADC）的比较器的第一输入端。 第一输入耦合到第一电容网络。 电路还包括用于ADC的比较器的第二输入。 第二输入耦合到第二电容网络。 第一电容网络包括第一组电容器，其中第一组电容器的第一板选择性地耦合到输入信号。 第二电容网络包括第二组电容器，其中第一组电容器的第二板选择性地耦合到输入信号。 第一板和第二板是第一组电容器和第二组电容器的相对的板。

    Analog-to-digital converter offset cancellation
    7.
    发明公开
    Analog-to-digital converter offset cancellation 审中-公开
    模拟数字-Wandler-Offsetunterdrückung

    公开(公告)号：EP2966780A1

    公开(公告)日：2016-01-13

    申请号：EP14306111.7

    申请日：2014-07-07

    申请人： STMicroelectronics International N.V.

    发明人： Vaccariello, Laurent

    IPC分类号： H03M1/06 ,  H03M1/40

    CPC分类号： H03M1/0663 ,  H03M1/0682 ,  H03M1/0695 ,  H03M1/403

    摘要： There is described a cyclic pipelined Analog-to-Digital Converter having an input (41) adapted to receive an analog voltage (V IN ) to be converted, and an output (42) adapted to deliver a n-bit digital value (N OUT ). The converter also comprises a core stage (40) comprising an Analog-to-Digital Conversion stage (50) to provide at least one bit value of the n-bit digital value at each one of a plurality of successive conversion steps performed in loop by the core stage (40). The core stage (40) further comprises a differential inputs-differential outputs amplifier (59). In order to cancel the offset of the stage (55, 58), the coupling of the amplifier inputs is inversed, i.e. the inputs are switched around, namely swapped, just after the first conversion step has been carried out. Simultaneously the differential outputs of the amplifier are similarly swapped.

    摘要翻译： 描述了具有适于接收要转换的模拟电压（V IN）的输入端（41）的循环流水线模数转换器和适于传送n位数字值（N OUT）的输出（42） ）。 转换器还包括核心级（40），其包括模数转换级（50），以在循环中以循环执行的多个连续转换步骤中的每一个提供n位数字值的至少一个位值 核心阶段（40）。 核心级（40）还包括差分输入差分输出放大器（59）。 为了消除级（55,58）的偏移，放大器输入的耦合被反转，即刚刚在执行第一转换步骤之后，输入被切换，即交换。 同时，放大器的差分输出也同样交换。

    A/D CONVERSION ARRAY AND IMAGE SENSOR
    8.
    发明公开
    A/D CONVERSION ARRAY AND IMAGE SENSOR 有权
    A / D转换阵列和图像传感器

    公开(公告)号：EP1679798A1

    公开(公告)日：2006-07-12

    申请号：EP04793319.7

    申请日：2004-10-27

    申请人： National University Corporation Shizuoka University

    发明人： KAWAHITO, Shoji

    IPC分类号： H03M1/40 ,  H04N5/335

    CPC分类号： H03M1/0695 ,  H03M1/403 ,  H04N5/357 ,  H04N5/378

    摘要： An A/D conversion array for an image sensor, in which the number of amplifiers and capacitors are decreased compared with the conventional cyclic type, and a function to cancel the noise generated in the pixel section of the image sensor is provided, so that the area and power consumption are decreased.
    After an input signal Vin is supplied to C1 and held, a reset level is applied to Vin, whereby the differential signal is amplified by the ratio of C1 and C2 (C1/C2) connected to an inverting amplifier. Then an output from the inverting amplifier is held in C1, and the output of the inverting amplifier is A/D-converted by a comparator so that a control signal is generated by the conversion output, and one of the switches controlled by φM1, φ01 and φP1 is turned ON. The digital signal is converted into an analog signal, and the analog signal is subtracted from the signal held in C1. This signal is amplified and is subjected to A/D conversion again, then the same operation is cyclically repeated. By this, noise cancellation and multi-bit A/D conversion can be performed.

    摘要翻译： 提供了一种用于图像传感器的A / D转换阵列，其中放大器和电容器的数量与传统的循环型相比减少了，并且提供了消除在图像传感器的像素部分中产生的噪声的功能， 面积和功耗下降。 在将输入信号Vin提供给C1并保持之后，复位电平被施加到Vin，由此差分信号被连接到反相放大器的C1和C2（C1 / C2）的比率放大。 然后，将来自反相放大器的输出保持在C1中，并且通过比较器对反相放大器的输出进行A / D转换，从而由转换输出生成控制信号，并且由φM1，φ01 φP1变为ON。 数字信号被转换成模拟信号，并从保持在C1中的信号中减去模拟信号。 该信号被放大并再次进行A / D转换，然后循环重复相同的操作。 由此，可以执行噪声消除和多位A / D转换。