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公开(公告)号：EP4429116A1
公开(公告)日：2024-09-11
申请号：EP21965945.5
申请日：2021-11-30
发明人： GAO, Peng , MAO, Yihong , TIAN, Hongliang
摘要： This application provides a phase-locked loop, a radio frequency transceiver, and a communication device, and relates to the field of communication technologies, to reduce power consumption of the communication device in a discontinuous working scenario. The phase-locked loop is configured to: output a first local oscillator signal in a first time period, where a phase of the first local oscillator signal at an end moment of the first time period is a first phase; disable the first local oscillator signal in a second time period; and output a second local oscillator signal in a third time period. The first time period, the second time period, and the third time period are three consecutive time periods in sequence, an angular frequency of the second local oscillator signal is the same as that of the first local oscillator signal, a phase of the second local oscillator signal at a start moment of the third time period is a second phase, a phase difference between the second phase and the first phase is equal to a product of the angular frequency and a time difference, and the time difference is a difference between the start moment of the third time period and the end moment of the first time period. The phase-locked loop is used in the communication device, to reduce power consumption of the communication device in the discontinuous working scenario.
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公开(公告)号：EP3158406A1
公开(公告)日：2017-04-26
申请号：EP15702273.2
申请日：2015-02-03
发明人： WU, Ying , STASZEWSKI, Robert , MAO, Yihong
CPC分类号： G04F10/005 , H03M3/414
摘要： A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.
摘要翻译： 时间 - 数字转换器（300,400）包括：用于接收时域输入信号（Tin）的输入（302,402）; 输出（306,406），用于提供数字输出信号（Dout）; 时间寄存器（305,405），其耦合到所述输入（302,403）并且耦合到第一节点（308,408）; 耦合到所述时间寄存器（305,405）的时间量化器（307,407），用于在所述输出（306,406）处提供所述数字输出信号（Dout）; 以及耦合到所述输出（306,406）用于在所述第一节点（308,408）处提供反馈信号（E，Qerr）的数字到时间转换器（309,409）。
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公开(公告)号：EP3502804A1
公开(公告)日：2019-06-26
申请号：EP18193113.0
申请日：2015-02-03
发明人： WU, Ying , STASZEWSKI, Robert , MAO, Yihong
摘要： A time-to-digital converter (300, 400) includes: an input (302, 402) for receiving a time-domain input signal (Tin); an output (306, 406) for providing a digital output signal (Dout); a time register (305, 405) coupled to the input (302, 403) and to a first node (308, 408); a time quantizer (307, 407) coupled to the time register (305, 405) for providing the digital output signal (Dout) at the output (306, 406); and a digital-to-time converter (309, 409) coupled to the output (306, 406) for providing a feed-back signal (E, Q err ) at the first node (308, 408).
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公开(公告)号：EP3158406B1
公开(公告)日：2018-10-03
申请号：EP15702273.2
申请日：2015-02-03
发明人： WU, Ying , STASZEWSKI, Robert , MAO, Yihong
CPC分类号： G04F10/005 , H03M3/414
摘要： A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.
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公开(公告)号：EP3502804B1
公开(公告)日：2020-07-22
申请号：EP18193113.0
申请日：2015-02-03
发明人： WU, Ying , STASZEWSKI, Robert , MAO, Yihong
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公开(公告)号：EP3149546B1
公开(公告)日：2019-04-10
申请号：EP15704250.8
申请日：2015-02-03
发明人： WU, Ying , STASZEWSKI, Robert , MAO, Yihong
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公开(公告)号：EP3149546A1
公开(公告)日：2017-04-05
申请号：EP15704250.8
申请日：2015-02-03
发明人： WU, Ying , STASZEWSKI, Robert , MAO, Yihong
CPC分类号： G04F10/005 , H03H19/004 , H03K5/135 , H03L7/0814 , H03L7/0891 , H03M1/00 , H03M1/12 , H03M1/1225 , H03M1/50 , H03M2201/4233
摘要： A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.
摘要翻译： 时间寄存器（300）包括：耦合到一对输入时钟（IN1，IN2）的一对输入（345,346）; 用于产生一对电平信号（VC1，VC2）的一对三态反相器（301,302）; 以及耦合到所述电平信号（VC1，VC2）的一对输出（347,348），用于产生一对输出时钟（OUT1，OUT2），其中所述三态反相器（301,302）响应于一对 状态信号（S1，S2）和用于保持或放电电平信号（VC1，VC2）的一对输入时钟（IN1，IN2）。
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