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    Method and circuit for bandwidth mismatch estimation in an a/d converter
    1.
    发明公开
    Method and circuit for bandwidth mismatch estimation in an a/d converter 有权
    的方法和电路用于在A / D转换器的带宽失配估计

    公开(公告)号：EP2953265A1

    公开(公告)日：2015-12-09

    申请号：EP14171580.5

    申请日：2014-06-06

    申请人： IMEC VZW

    发明人： Deguchi, Kazuaki ,  Verbruggen, Bob ,  Craninckx, Jan

    IPC分类号： H03M1/10 ,  H03M1/12

    CPC分类号： H03M1/0604 ,  H03M1/00 ,  H03M1/002 ,  H03M1/1071 ,  H03M1/109 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/14 ,  H03M1/468 ,  H03M2201/4233

    摘要： The invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter (10) comprising
    - precharging to a first state second terminals of capacitors (3) in each channel (1) of a plurality of channels and sampling (2) a reference analog input voltage signal (V ref ) applied via a first switchable path (6) whereby the sampled input voltage signal is received at first terminals of said capacitors,
    - setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff ) at said first terminals,
    - applying said reference analog input voltage signal to said first terminals via a second switchable path (7), said second path having a given impedance being higher than the known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal,
    - quantizing said settling error, thereby obtaining an estimate of the non-zero settling error in each channel,
    - comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch.

    TIME REGISTER
    3.
    发明公开
    TIME REGISTER 审中-公开
    ZEITREGISTER

    公开(公告)号：EP3149546A1

    公开(公告)日：2017-04-05

    申请号：EP15704250.8

    申请日：2015-02-03

    申请人： Huawei Technologies Co. Ltd.

    发明人： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

    IPC分类号： G04F10/00 ,  H03M1/50

    CPC分类号： G04F10/005 ,  H03H19/004 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/50 ,  H03M2201/4233

    摘要： A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

    摘要翻译： 时间寄存器（300）包括：耦合到一对输入时钟（IN1，IN2）的一对输入（345,346）; 用于产生一对电平信号（VC1，VC2）的一对三态反相器（301,302）; 以及耦合到所述电平信号（VC1，VC2）的一对输出（347,348），用于产生一对输出时钟（OUT1，OUT2），其中所述三态反相器（301,302）响应于一对 状态信号（S1，S2）和用于保持或放电电平信号（VC1，VC2）的一对输入时钟（IN1，IN2）。