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公开(公告)号:EP4451568A1
公开(公告)日:2024-10-23
申请号:EP24163598.6
申请日:2024-03-14
发明人: STILGENBAUER, Francesco , BOTTI, Edoardo , MALCOVATI, Piero , CROVETTI, Paolo Stefano , BONIZZONI, Edoardo , DE FERRARI, Matteo
摘要: A delta-sigma modulator (110) includes a loop filter circuit (114) having a first input that receives an input signal (102) and a second input that receives a feedback signal (105). The loop filter (114) circuit generates a filtered signal (106). A quantizer circuit (124) quantizes the filtered signal (106) to generate an output signal (103). An anti-windup circuit (112) detects instances where the filtered signal (106) is outside an input signal input of the quantizer circuit (124) and in response thereto generates a dead zone signal (107) having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal (105) is a sum of the output signal (103) and the dead zone signal (107).
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公开(公告)号:EP4429118A1
公开(公告)日:2024-09-11
申请号:EP24159995.0
申请日:2024-02-27
发明人: Ragab, Kareem , Lin, Xiaofeng , Cheung, Darwin , Mo, Chi , Chandrasekhar, Vinay , Song, Jungwoo , Jiang, Xicheng
CPC分类号: H03M1/468 , H03M1/0854 , H03M1/687 , H03M1/804 , H03M1/066 , H03M1/0673 , H03M3/39 , H03M3/338 , H03M3/35 , H03M1/0678
摘要: A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.
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公开(公告)号:EP4415268A1
公开(公告)日:2024-08-14
申请号:EP23156114.3
申请日:2023-02-10
申请人: NXP B.V.
发明人: Hardeman,, Gijsbert Willem , Rutten,, Robert , Pol,, Evert-Jan Daniel , Liu,, Qilong , Bajoria,, Shagun , Breems,, Lucien Johannes
CPC分类号: H03M1/1033 , H03M1/14 , H03M3/414
摘要: A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.
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公开(公告)号:EP4272317A1
公开(公告)日:2023-11-08
申请号:EP21848089.5
申请日:2021-12-28
发明人: WEN, Bing , HONG, John , CHAN, Edward
IPC分类号: H03M3/00
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公开(公告)号:EP4073935B1
公开(公告)日:2023-09-06
申请号:EP20807518.4
申请日:2020-11-12
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公开(公告)号:EP4193466A1
公开(公告)日:2023-06-14
申请号:EP21790781.5
申请日:2021-08-05
发明人: RITTER, Rudolf
IPC分类号: H03M3/00
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公开(公告)号:EP4188620A1
公开(公告)日:2023-06-07
申请号:EP21752485.9
申请日:2021-07-27
发明人: ZHANG, Ming , LLASER, Nicolas
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