公开(公告)号：EP3025239B1

公开(公告)日：2018-12-26

申请号：EP13890241.6

申请日：2013-07-26

申请人： Intel Corporation

发明人： OOI, Eng Hun ,  ROYER, Robert J. ,  WILLIAMS, Michael W. ,  WILCOX, Jeffrey R. ,  TRIVEDI, Ritesh B. ,  FANNING, Blaise

IPC分类号： G06F13/16 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：EP1461706B1

公开(公告)日：2009-05-13

申请号：EP02794434.7

申请日：2002-12-27

申请人： Intel Corporation

发明人： KHAN, Opher D. ,  WILCOX, Jeffrey R.

IPC分类号： G06F12/02

CPC分类号： G06F12/0215

摘要： A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.

公开(公告)号：EP1461706A1

公开(公告)日：2004-09-29

申请号：EP02794434.7

申请日：2002-12-27

申请人： INTEL CORPORATION

发明人： KHAN, Opher D. ,  WILCOX, Jeffrey R.

IPC分类号： G06F12/02

CPC分类号： G06F12/0215

摘要： A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.