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    RECONFIGURABLE CLOCKING ARCHITECTURE
    3.
    发明公开
    RECONFIGURABLE CLOCKING ARCHITECTURE 审中-公开

    公开(公告)号：EP3417455A1

    公开(公告)日：2018-12-26

    申请号：EP17753613.3

    申请日：2017-01-17

    申请人： Intel Corporation

    发明人： MANSURI, Mozhgan ,  MARTIN, Aaron ,  MCCALL, James A.

    IPC分类号： G11C11/4076 ,  G11C7/22 ,  H03K3/03 ,  G05F1/575

    CPC分类号： G11C11/4076 ,  G06F1/10 ,  G06F13/4234 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4093 ,  H03K5/14 ,  H03K2005/00052 ,  H04L7/0337

    摘要： Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

    REDUCING SIMULTANEOUS SWITCHING OUTPUTS USING DATA BUS INVERSION SIGNALING
    9.
    发明授权
    REDUCING SIMULTANEOUS SWITCHING OUTPUTS USING DATA BUS INVERSION SIGNALING 有权
    用数据总线反向信号减少同步开关输出

    公开(公告)号：EP2558945B1

    公开(公告)日：2014-12-10

    申请号：EP11717063.9

    申请日：2011-04-05

    申请人： Advanced Micro Devices Inc.

    发明人： DEARTH, Glenn, A. ,  PATEL, Shwetal, A.

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4234 ,  Y02D10/14 ,  Y02D10/151

    摘要： An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.