公开(公告)号：EP0039784A1

公开(公告)日：1981-11-18

申请号：EP81102644.2

申请日：1981-04-08

申请人： International Business Machines Corporation

发明人： Barkley, Keith Gustav ,  Ghafghaichi, Majid ,  Gopalakrishna, Yelandur Ranganatha ,  Tzou, Albert Ji-shou

IPC分类号： G11C19/28

CPC分类号： H01L27/1057 ,  G11C19/287

摘要： This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register (14) with gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers (12) to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order.