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    Non-volatile DRAM cell
    2.
    发明公开
    Non-volatile DRAM cell 失效
    非易失性DRAM单元

    公开(公告)号：EP0557581A3

    公开(公告)日：1994-11-17

    申请号：EP92118487.5

    申请日：1992-10-29

    申请人： International Business Machines Corporation

    发明人： Acovic, Alexandre ,  Hsu, Ching-Hsiang, Dep. Of Electrical Engineering ,  Wordeman, Matthew Robert ,  Wu, Being Song

    IPC分类号： G11C14/00 ,  H01L29/788

    CPC分类号： B82Y10/00 ,  G11C14/00

    摘要： The present invention is directed to a one-transistor non-volatile DRAM cell (10, 40, 66, 79) having a two layer floating gate (14) to allow the contents of a storage capacitor (28) to be transferred to the floating gate (14) during power interruptions. The first layer (18) of the floating gate (14) is separated from a storage node (32) of the storage capacitor (28) by a tunnel oxide (92) to allow electron tunnelling between the floating gate (14) and the storage capacitor (32). In another embodiment of the present invention, a dual electron injector structure (44) is disposed between a one layer floating gate (42) and the storage node (32) to allow electrons to be injected between the floating gate (42) and the storage node (32). In another embodiment of the present invention, an erase gate (70) is implemented to remove the charge on the floating gate (14, 42). The erase gate (70) can be separated from the floating gate (14, 42) by a tunnel oxide (92) or a single electron injector structure (44) to allow electrons to travel from the floating gate (14, 42) to the erase gate (70).

    Data output drivers with pull-up devices
    6.
    发明公开
    Data output drivers with pull-up devices 失效
    。。。。。。。。。。。。。

    公开(公告)号：EP0678800A2

    公开(公告)日：1995-10-25

    申请号：EP95104379.3

    申请日：1995-03-24

    申请人： International Business Machines Corporation

    发明人： Dhong, Sang H. ,  Kirihata, Toshiaki ,  Wordeman, Matthew Robert

    IPC分类号： G05F3/24

    CPC分类号： G05F3/24

    摘要： A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

    摘要翻译： 用于控制跨越NMOS上拉晶体管的电压的装置，其包括可能暴露于可变电压的源节点。 该器件还包括可以暴露于可变电压的栅极节点。 控制部分调节施加到栅极节点的电压，其中源极节点和栅极节点之间的电压差被限制到期望的电平。

    Non-volatile DRAM cell
    7.
    发明公开
    Non-volatile DRAM cell 失效
    NichtflüchtigeDRAM-Zelle。

    公开(公告)号：EP0557581A2

    公开(公告)日：1993-09-01

    申请号：EP92118487.5

    申请日：1992-10-29

    申请人： International Business Machines Corporation

    发明人： Acovic, Alexandre ,  Hsu, Ching-Hsiang, Dep. Of Electrical Engineering ,  Wordeman, Matthew Robert ,  Wu, Being Song

    IPC分类号： G11C14/00 ,  H01L29/788

    CPC分类号： B82Y10/00 ,  G11C14/00

    摘要： The present invention is directed to a one-transistor non-volatile DRAM cell (10, 40, 66, 79) having a two layer floating gate (14) to allow the contents of a storage capacitor (28) to be transferred to the floating gate (14) during power interruptions. The first layer (18) of the floating gate (14) is separated from a storage node (32) of the storage capacitor (28) by a tunnel oxide (92) to allow electron tunnelling between the floating gate (14) and the storage capacitor (32). In another embodiment of the present invention, a dual electron injector structure (44) is disposed between a one layer floating gate (42) and the storage node (32) to allow electrons to be injected between the floating gate (42) and the storage node (32). In another embodiment of the present invention, an erase gate (70) is implemented to remove the charge on the floating gate (14, 42). The erase gate (70) can be separated from the floating gate (14, 42) by a tunnel oxide (92) or a single electron injector structure (44) to allow electrons to travel from the floating gate (14, 42) to the erase gate (70).

    摘要翻译： 本发明涉及一种具有双层浮动栅极（14）的单晶体管非易失性DRAM单元（10,40,66,79），以便将存储电容器（28）的内容传输到浮置 电源中断时门（14）。 浮动栅极（14）的第一层（18）通过隧道氧化物（92）与存储电容器（28）的存储节点（32）分离，以允许浮动栅极（14）和存储器 电容器（32）。 在本发明的另一实施例中，双电子注入器结构（44）设置在单层浮动栅极（42）和存储节点（32）之间，以允许电子注入浮置栅极（42）和存储器 节点（32）。 在本发明的另一个实施例中，实现擦除栅极（70）以去除浮动栅极（14,42）上的电荷。 擦除栅极（70）可以通过隧道氧化物（92）或单个电子注入器结构（44）与浮动栅极（14,42）分离，以允许电子从浮动栅极（14,42）行进到 擦除门（70）。

    Radiation tolerant semiconductor device and method of making such a device
    9.
    发明公开
    Radiation tolerant semiconductor device and method of making such a device 失效
    Strahlungsunempfindliches Halbleiterbauelement和Verfahren zu seiner Herstellung。

    公开(公告)号：EP0066065A1

    公开(公告)日：1982-12-08

    申请号：EP82102984.0

    申请日：1982-04-07

    申请人： International Business Machines Corporation

    发明人： Dennard, Robert Heath ,  Wordeman, Matthew Robert

    IPC分类号： H01L29/06 ,  H01L21/74

    CPC分类号： H01L21/74 ,  H01L23/556 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A radiation tolerant semiconductor device has a buried grid (11) of enhanced concentration of an impurity type opposite to that of the semiconductor substrate. Such a device may be made by providing beneath the upper surface of a semiconductor substrate a continuous region (12, 13) of a first impurity type which is the same as that of the semiconductor substrate, the region having an array of regularly spaced via portions (13) at a depth beneath the surface greater than the depth of the remainder of the region (12), and providing at a depth substantially coincident with the via portions (13) a second impurity of conductivity type opposite to that of the first impurity at a dosage level lower than that of the first impurity to form the buried grid (11).

    摘要翻译： 耐辐射半导体器件具有与半导体衬底相反的杂质类型的增强浓度的埋入栅格（11）。 可以通过在半导体衬底的上表面下方设置与半导体衬底相同的第一杂质类型的连续区域（12,13）来制造这种器件，该区域具有规则间隔的通孔部分 （13），其深度大于所述区域（12）的其余部分的深度，并且在与所述通孔部分（13）基本重合的深度处提供与所述第一杂质相反的第二导电类型杂质 其剂量水平低于第一杂质的剂量水平以形成掩埋栅格（11）。