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公开(公告)号：EP0562307A3
公开(公告)日：1994-09-07
申请号：EP93103255.1
申请日：1993-03-02
IPC分类号： H01L27/115 , H01L29/788 , H01L21/82 , G11C16/04
CPC分类号： H01L27/10844 , G11C16/12 , G11C16/14 , H01L27/115 , H01L29/66825 , H01L29/7883
摘要： The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region (103) of the transfer FET of the EEPROM cell. The heavily doped source and drain regions (47,50) are formed on two vertical sidewalls of the trench (45) and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region (103) is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench (45) are formed by isolation oxide (70). A first silicon dioxide layer covers the bottom of the trench (45) and forms part of the gate oxide (105) of the cell device. A second silicon dioxide layer (100) covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer (105). The second silicon dioxide layer (100) separates the source and drain regions (47,50) from the floating gate (110) which overlays both the first and second silicon dioxide layers. The floating gate (110) overlaps all four trench sidewalls and substantially increases the coupling between the floating gate (110) and a control gate (40). The control gate (40) overlies the floating gate (110) and the control gate is separated from the floating gate by a separate dielectric layer (115). The second silicon dioxide layer (100) is relatively thin so that tunneling of electrons between the vertical sidewalls which incorpoate the source and drain regions (47,50) and the floating gate (110) will occur. Tunnelling is the mechanism which charges and discharges the floating gate. The trench EEPROM memory structure occupies a small amount of surface are a while maintaining a high coupling ratio between the control gate (40) and the floating gate (110). The high coupling ratio between the floating gate and the control gate is maintained because the floating gate is butted to isolation oxide on two sides of the trench. The trench EEPROM memory structure of the present invention also reduces program and erase time because the floating gate can be programmed or charged through either the source or drain regions in many cells at one time.
摘要翻译： 本发明的目的是通过将MOSFET器件和浮置栅极合并成三维沟槽结构来实现的。 沟槽器件单元具有四个垂直侧面和底部。 沟槽的底部形成EEPROM单元的转移FET的沟道区域（103）。 重掺杂源极和漏极区域（47,50）形成在沟槽（45）的两个垂直侧壁上并且彼此相对。 重掺杂区域覆盖整个侧壁并且具有大于沟槽深度的深度，使得沟道区域（103）由沟槽的底部限定。 沟槽（45）的其余两个垂直侧壁由隔离氧化物（70）形成。 第一二氧化硅层覆盖沟槽（45）的底部并形成电池器件的栅极氧化物（105）的一部分。 第二二氧化硅层（100）覆盖沟槽的垂直侧壁。 第二二氧化硅层相对于栅极氧化物层（105）相对较薄。 第二二氧化硅层（100）将源极区域和漏极区域（47,50）与覆盖第一二氧化硅层和第二二氧化硅层两者的浮置栅极（110）分隔开。 浮动栅极（110）与全部四个沟槽侧壁重叠并且实质上增加浮动栅极（110）与控制栅极（40）之间的耦合。 控制栅极（40）覆盖浮置栅极（110）并且控制栅极通过单独的电介质层（115）与浮置栅极分隔开。 第二二氧化硅层（100）相对较薄，使得在包含源极和漏极区域（47,50）和浮置栅极（110）的垂直侧壁之间发生隧穿电子。 隧道是充电和放电浮动门的机制。 沟槽EEPROM存储器结构占据少量表面的同时保持控制栅极（40）和浮动栅极（110）之间的高耦合比。 由于浮置栅极与沟槽两侧的隔离氧化物对接，所以保持了浮置栅极和控制栅极之间的高耦合比。 本发明的沟槽EEPROM存储器结构还减少了编程和擦除时间，因为浮动栅极可以通过一次在许多单元中的源极或漏极区域被编程或充电。
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公开(公告)号：EP0557581A3
公开(公告)日：1994-11-17
申请号：EP92118487.5
申请日：1992-10-29
发明人： Acovic, Alexandre , Hsu, Ching-Hsiang, Dep. Of Electrical Engineering , Wordeman, Matthew Robert , Wu, Being Song
IPC分类号： G11C14/00 , H01L29/788
摘要： The present invention is directed to a one-transistor non-volatile DRAM cell (10, 40, 66, 79) having a two layer floating gate (14) to allow the contents of a storage capacitor (28) to be transferred to the floating gate (14) during power interruptions. The first layer (18) of the floating gate (14) is separated from a storage node (32) of the storage capacitor (28) by a tunnel oxide (92) to allow electron tunnelling between the floating gate (14) and the storage capacitor (32). In another embodiment of the present invention, a dual electron injector structure (44) is disposed between a one layer floating gate (42) and the storage node (32) to allow electrons to be injected between the floating gate (42) and the storage node (32). In another embodiment of the present invention, an erase gate (70) is implemented to remove the charge on the floating gate (14, 42). The erase gate (70) can be separated from the floating gate (14, 42) by a tunnel oxide (92) or a single electron injector structure (44) to allow electrons to travel from the floating gate (14, 42) to the erase gate (70).
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公开(公告)号：EP0562307A2
公开(公告)日：1993-09-29
申请号：EP93103255.1
申请日：1993-03-02
IPC分类号： H01L27/115 , H01L29/788 , H01L21/82 , G11C16/04
CPC分类号： H01L27/10844 , G11C16/12 , G11C16/14 , H01L27/115 , H01L29/66825 , H01L29/7883
摘要： The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region (103) of the transfer FET of the EEPROM cell. The heavily doped source and drain regions (47,50) are formed on two vertical sidewalls of the trench (45) and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region (103) is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench (45) are formed by isolation oxide (70). A first silicon dioxide layer covers the bottom of the trench (45) and forms part of the gate oxide (105) of the cell device. A second silicon dioxide layer (100) covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer (105). The second silicon dioxide layer (100) separates the source and drain regions (47,50) from the floating gate (110) which overlays both the first and second silicon dioxide layers. The floating gate (110) overlaps all four trench sidewalls and substantially increases the coupling between the floating gate (110) and a control gate (40). The control gate (40) overlies the floating gate (110) and the control gate is separated from the floating gate by a separate dielectric layer (115). The second silicon dioxide layer (100) is relatively thin so that tunneling of electrons between the vertical sidewalls which incorpoate the source and drain regions (47,50) and the floating gate (110) will occur. Tunnelling is the mechanism which charges and discharges the floating gate. The trench EEPROM memory structure occupies a small amount of surface are a while maintaining a high coupling ratio between the control gate (40) and the floating gate (110). The high coupling ratio between the floating gate and the control gate is maintained because the floating gate is butted to isolation oxide on two sides of the trench. The trench EEPROM memory structure of the present invention also reduces program and erase time because the floating gate can be programmed or charged through either the source or drain regions in many cells at one time.
摘要翻译： 本发明的目的是通过将MOSFET器件和浮置栅极合并成三维沟槽结构来实现的。 沟槽器件单元具有四个垂直边和底部。 沟槽的底部形成EEPROM单元的传送FET的沟道区（103）。 重掺杂源极和漏极区域（47,50）形成在沟槽（45）的两个垂直侧壁上并相对地彼此面对。 重掺杂区域覆盖整个侧壁并且具有大于沟槽深度的深度，使得沟道区域（103）由沟槽的底部限定。 沟槽（45）的剩余两个垂直侧壁由隔离氧化物（70）形成。 第一二氧化硅层覆盖沟槽（45）的底部并形成电池器件的栅极氧化物（105）的一部分。 第二二氧化硅层（100）覆盖沟槽的垂直侧壁。 第二二氧化硅层相对于栅极氧化物层（105）相对较薄。 第二二氧化硅层（100）将源极和漏极区域（47,50）与覆盖第一和第二二氧化硅层的浮置栅极（110）分离。 浮置栅极（110）与所有四个沟槽侧壁重叠，并且基本上增加了浮动栅极（110）和控制栅极（40）之间的耦合。 控制栅极（40）覆盖浮置栅极（110），并且控制栅极通过单独的介电层（115）与浮动栅极分离。 第二二氧化硅层（100）相对较薄，使得电子在引起源极和漏极区域（47,50）和浮动栅极（110）的垂直侧壁之间的隧穿将发生。 隧道是对浮闸进行充放电的机制。 占用少量表面的沟槽EEPROM存储器结构同时保持控制栅极（40）和浮动栅极（110）之间的高耦合比。 保持浮栅和控制栅之间的高耦合比，因为浮栅与沟槽两侧的隔离氧化物对接。 本发明的沟槽EEPROM存储器结构还减少了编程和擦除时间，因为浮动栅极可以通过多个单元中的源极或漏极区域一次被编程或充电。
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公开(公告)号：EP0557581A2
公开(公告)日：1993-09-01
申请号：EP92118487.5
申请日：1992-10-29
发明人： Acovic, Alexandre , Hsu, Ching-Hsiang, Dep. Of Electrical Engineering , Wordeman, Matthew Robert , Wu, Being Song
IPC分类号： G11C14/00 , H01L29/788
摘要： The present invention is directed to a one-transistor non-volatile DRAM cell (10, 40, 66, 79) having a two layer floating gate (14) to allow the contents of a storage capacitor (28) to be transferred to the floating gate (14) during power interruptions. The first layer (18) of the floating gate (14) is separated from a storage node (32) of the storage capacitor (28) by a tunnel oxide (92) to allow electron tunnelling between the floating gate (14) and the storage capacitor (32). In another embodiment of the present invention, a dual electron injector structure (44) is disposed between a one layer floating gate (42) and the storage node (32) to allow electrons to be injected between the floating gate (42) and the storage node (32). In another embodiment of the present invention, an erase gate (70) is implemented to remove the charge on the floating gate (14, 42). The erase gate (70) can be separated from the floating gate (14, 42) by a tunnel oxide (92) or a single electron injector structure (44) to allow electrons to travel from the floating gate (14, 42) to the erase gate (70).
摘要翻译： 本发明涉及一种具有双层浮动栅极（14）的单晶体管非易失性DRAM单元（10,40,66,79），以便将存储电容器（28）的内容传输到浮置 电源中断时门（14）。 浮动栅极（14）的第一层（18）通过隧道氧化物（92）与存储电容器（28）的存储节点（32）分离，以允许浮动栅极（14）和存储器 电容器（32）。 在本发明的另一实施例中，双电子注入器结构（44）设置在单层浮动栅极（42）和存储节点（32）之间，以允许电子注入浮置栅极（42）和存储器 节点（32）。 在本发明的另一个实施例中，实现擦除栅极（70）以去除浮动栅极（14,42）上的电荷。 擦除栅极（70）可以通过隧道氧化物（92）或单个电子注入器结构（44）与浮动栅极（14,42）分离，以允许电子从浮动栅极（14,42）行进到 擦除门（70）。
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