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    High voltage complementary NPN/PNP process
    3.
    发明公开
    High voltage complementary NPN/PNP process 失效
    高压补充NPN / PNP工艺

    公开(公告)号：EP0401716A3

    公开(公告)日：1992-07-08

    申请号：EP90110523.9

    申请日：1990-06-02

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Jennings, Dean ,  Buynoski, Matthew

    IPC分类号： H01L21/331

    CPC分类号： H01L27/0826 ,  H01L21/761 ,  H01L21/82285

    摘要： A process is disclosed for forming high-performance, high voltage PNP and NPN power transistors in a conventional monolithic, planar, epitaxial PNP junction isolated integrated circuit. The process permits independently optimizing the NPN and PNP power transistors. Where high-voltage devices are desired a field threshold adjustment implant is applied. It also includes provisions for testing critical portions of the process at appropriate points.

    High voltage complementary NPN/PNP process
    4.
    发明公开
    High voltage complementary NPN/PNP process 失效
    Verfahren zur Herstellung vonkomplementärenNPN / PNP hoher Spannung。

    公开(公告)号：EP0401716A2

    公开(公告)日：1990-12-12

    申请号：EP90110523.9

    申请日：1990-06-02

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Jennings, Dean ,  Buynoski, Matthew

    IPC分类号： H01L21/331

    CPC分类号： H01L27/0826 ,  H01L21/761 ,  H01L21/82285

    摘要： A process is disclosed for forming high-performance, high voltage PNP and NPN power transistors in a conventional monolithic, planar, epitaxial PNP junction isolated integrated circuit. The process permits independently optimizing the NPN and PNP power transistors. Where high-voltage devices are desired a field threshold adjustment implant is applied. It also includes provisions for testing critical portions of the process at appropriate points.

    摘要翻译： 公开了一种用于在传统的单片，平面，外延PNP结隔离集成电路中形成高性能，高电压PNP和NPN功率晶体管的工艺。 该过程允许独立地优化NPN和PNP功率晶体管。 在需要高电压装置的场合，应用场阈值调整植入。 它还包括在适当的点测试过程的关键部分的规定。

    Method of forming a localized buried isolation structure
    6.
    发明公开
    Method of forming a localized buried isolation structure 失效
    用于超高能量注入和使用这种方法的用于局部埋入注入和隔离结构Selbstaligniertes标记方法。

    公开(公告)号：EP0460440A2

    公开(公告)日：1991-12-11

    申请号：EP91108017.4

    申请日：1991-05-17

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Aronowitz, Sheldon ,  Hart, Courtney L. ,  Buynoski, Matthew

    IPC分类号： H01L21/266 ,  H01L21/76 ,  H01L21/316

    CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/266 ,  H01L21/31662 ,  H01L21/74 ,  Y10S438/945 ,  Y10S438/95 ,  Y10S438/966

    摘要： A self-aligned masking process for use with ultra-high energy implants (implant energies equal to or greater than 1 MeV) is provided. The process can be applied to an arbitrary range of implant energies. Consequently, high doses of dopant may be implanted to give high concentrations that are deeply buried. This can be coupled with the fact that amorphization of the substrate lattice is relatively localized to the region where the ultra-high energy implant has peaked to yield a procedure to form buried, localized isolation structures.

    摘要翻译： 提供了一种用于超高能量植入物（植入能量等于或大于1兆电子伏）中使用的自对准掩模工艺。 该方法可在植入能量的任意范围被应用于。 因此，高剂量的掺杂剂的可植入给予高浓度也被深埋。 这可与基板的晶格的factthat非晶化相对定位于其中所述超高能植入物已经达到顶峰，得到一个过程来形成掩埋区域中，局部的隔离结构。